P5020NSN1VNB Freescale Semiconductor, P5020NSN1VNB Datasheet - Page 150

• Manufacturer Part Number: P5020NSN1VNB
• Description: Processors - Application Specialized P5020 Std Tmp NoEnc 2000/1333 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5020NSN1VNB

• Rohs: yes

Hardware Design Considerations
150
2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved
6. Asserting HRESET causes a hard reset on the device.
1. The COP port and target board must be able to independently assert PORESET and TRST to the processor
5.This switch is included as a precaution for BSDL testing. The switch must be closed to position A during BSDL testing
Notes:
signal integrity.
to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch must be closed
to position B.
COP Connector
Physical Pinout
in order to fully control the processor as shown here.
11
13
15
1
1
3
5
7
9
Board Sources
No pin
From Target
KEY
10
12
16
4
6
8
2
(if any)
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
PORESET
14
13
11
10
12
16
HRESET
15
4
6
5
8
9
1
3
7
2
Figure 59. Legacy JTAG Interface Connection
3
COP_CHKSTP_OUT
COP_VDD_SENSE
COP_CHKSTP_IN
COP_TMS
COP_TDO
COP_TDI
COP_TCK
COP_SRESET
COP_TRST
COP_HRESET
NC
NC
NC
4
B
2
5
A
System logic
10 Ω
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
OV
DD
HRESET
PORESET
TRST
CKSTP_OUT
TMS
TDO
TDI
TCK
Freescale Semiconductor
P5020/P5010
1
6
1