P5020NSN1VNB Freescale Semiconductor, P5020NSN1VNB Datasheet - Page 140

• Manufacturer Part Number: P5020NSN1VNB
• Description: Processors - Application Specialized P5020 Std Tmp NoEnc 2000/1333 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5020NSN1VNB

• Rohs: yes

Hardware Design Considerations
The RCW Configuration field DDR_RSV0 (bit 234) must be set to b’0 for all ratios.
In synchronous mode, the DDR data rate to platform clock ratios supported are listed in this table. This ratio is determined by
the binary value of the RCW Configuration field MEM_PLL_RAT[10:14].
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Note:
Note:
1. Set MEM_PLL_CFG=0b01 if the applied DDR PLL reference clock (Platform clock) frequency is greater than given cutoff,
1. Set RCW field MEM_PLL_CFG = 0b01 if the applied DDR PLL reference clock (SYSCLK) frequency is greater than given
Binary Value of MEM_PLL_RAT[10:14]
cutoff, else set to 0b00 for frequency that is less than or equal to cutoff.
else set to 0b00 for frequency that is less than or equal to cutoff.
MEM_PLL_RAT[10:14]
Binary Value of
All Others
0_0001
All Others
0_0101
0_0110
0_1000
0_1001
0_1010
0_1100
0_1101
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
Table 103. Asynchronous DDR Clock Ratio
Table 104. Synchronous DDR Clock Ratio
DDR:Platform CLK Ratio
Reserved
DDR:SYSCLK Ratio
1:1
Reserved
10:1
12:1
13:1
5:1
6:1
8:1
9:1
Set MEM_PLL_CFG=01 for Platform CLK Freq
Set MEM_PLL_CFG = 01 for SYSCLK Freq
>600 MHz
>120.9 MHz
>107.4 MHz
>96.7 MHz
>80.6 MHz
>96.7 MHz
>80.6 MHz
>74.4 MHz
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Freescale Semiconductor
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