MCIMX6U7CVM08AB Freescale Semiconductor, MCIMX6U7CVM08AB Datasheet - Page 76

• Manufacturer Part Number: MCIMX6U7CVM08AB
• Description: Processors - Application Specialized i.MX6 DualLite
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6U7CVM08AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Data Ram Size: 128 KB
• Maximum Operating Temperature: + 105
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-624
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

1
2
Electrical Characteristics
4.11.2.1 ECSPI Master Mode Timing
Figure 38
characteristics.
76
RDY
SSx
SCLK
MOSI
MISO
See specific I/O AC parameters
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
CS10
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
ID
CS10
depicts the timing of ECSPI in master mode.
SCLK Cycle Time–Read
SCLK Cycle Time–Write
SCLK High or Low Time–Read
SCLK High or Low Time–Write
SCLK Rise or Fall
SSx pulse width
SSx Lead Time (CS setup time)
SSx Lag Time (CS hold time)
MOSI Propagation Delay (C
MISO Setup Time
MISO Hold Time
RDY to SSx Time
CS8
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
CS1
2
1
Parameter
CS7
CS9
Table 50. ECSPI Master Mode Timing Parameters
Section 4.7, “I/O AC Parameters.”
Figure 38. ECSPI Master Mode Timing Diagram
CS3
LOAD
CS3
= 20 pF)
t
RISE/FALL
Symbol
t
PDmosi
t
t
t
t
t
Smiso
Hmiso
CSLH
t
SDRY
t
HCS
t
SCS
SW
clk
Table 50
CS2
CS2
Half SCLK period - 4
Half SCLK period - 2
lists the ECSPI master mode timing
Half SCLK period
21.5
Min
43
15
18
—
-1
7
0
5
CS6
CS4
Freescale Semiconductor
Max
—
—
—
—
—
—
—
—
—
1
CS5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns