MCIMX6L3DVN10AA Freescale Semiconductor, MCIMX6L3DVN10AA Datasheet - Page 43

• Manufacturer Part Number: MCIMX6L3DVN10AA
• Description: Processors - Application Specialized i.MX6 Megrez
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6L3DVN10AA

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 128 KB
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-432
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: 0 C
• Number Of Timers: 2

4.8.3
The LPDDR2 interface fully complies with JESD209-2B LPDDR2 JEDEC standard release June, 2009.
The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008.
Table 32
Note:
1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.
2. Calibration is done against 240 W external reference resistor.
3. Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.
4.9
This section contains the timing and electrical parameters for the modules in each i.MX 6SoloLite
processor.
4.9.1
Figure 8
Freescale Semiconductor
Output Driver
Impedance
Parameter
shows the reset timing and
shows DDR I/O output buffer impedance of i.MX 6SoloLite processor.
System Modules Timing
DDR I/O Output Buffer Impedance
Reset Timings Parameters
i.MX 6SoloLite Applications Processors for Consumer Products, Rev. 1
(Input)
Symbol
POR_B
Rdrv
Drive Strength (DSE) =
000
001
010
011
100
101
110
111
Table 32. DDR I/O Output Buffer Impedance
Test Conditions
Table 33
Figure 8. Reset Timing Diagram
lists the timing parameters.
CC1
NVCC_DRAM=1.5 V
DDR_SEL=11
(DDR3)
Hi-Z
240
120
80
60
48
40
34
Typical
NVCC_DRAM=1.2 V
DDR_SEL=10
(LPDDR2)
Hi-Z
240
120
80
60
48
40
34
Electrical Characteristics
Unit
Ω
43