MC10XS3535DHFKR2 Freescale Semiconductor, MC10XS3535DHFKR2 Datasheet - Page 31

• Manufacturer Part Number: MC10XS3535DHFKR2
• Description: Power Switch ICs - Power Distribution PENTA Output ESWITCH
• Manufacturer: Freescale Semiconductor

Specifications of MC10XS3535DHFKR2

• Rohs: yes
• Number Of Outputs: 5
• On Resistance (max): 55 mOhms
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: PQFN-24
• Minimum Operating Temperature: - 40 C
• Output Current: 250 mA

ADDRESS 00011 — CONFIGURATION CSNS
disable the high over-current shutdown phase (OCHI1 and
OCHI2 dynamic levels) in order to activate immediately the
current sense analog feedback.
synchronization signal is reported on FETOUT output pin.
the output is only protected with OCLO level. And the current
sense is immediately available if it is selected through SPI, as
described in
automatically reset at each corresponding ONoff bit transition
from logic [1] to [0] and in case of over-temperature or over-
current fault. All NO_OCHI bits are also reset in case of
under-voltage fault detection.
ADDRESS 01001 — CONTROL OUT1
Table
with bit D7 at logic [0]. This register allows the master to
control the duty cycle and the switching phases of OUT1. The
duty cycle resolution is given by bits D6 : D0.
period.
ADDRESS 01010 — CONTROL OUT2
ADDRESS 01011 — CONTROL OUT3
ADDRESS 01100 — CONTROL OUT4
ADDRESS 01101 — CONTROL OUT5
Analog Integrated Circuit Device Data
Freescale Semiconductor
The Configuration Current Sense register is used to
When bit D9 is set to logic [1], the current sense
When the corresponding NO_OCHI bit is set to logic [1],
Bits D9 and D8 control the switching phases as shown in
Bit D7 at logic [1] turns ON OUT1. OUT1 is turned OFF
D7 = 0, D6 : D0 = XX output OFF.
D7 = 1, D6 : D0 = 00 output ON during 1/128.
D7 = 1, D6 : D0 = 1A output ON during 27/128 on PWM
D7 = 1, D6 : D0 = 7F output continuous ON (no PWM).
Same description as OUT1.
Same description as OUT1.
Same description as OUT1.
Same description as OUT1.
10.
Figures
D9 : D8
Table 10. Switching Phases
00
01
10
11
13. The NO_OCHI bit per output is
PWM Phase
180°
270°
90°
0°
ADDRESS 01110 — CONTROL EXTERNAL SWITCH
ADDRESS 01111 — TEST MODE
SPI during normal operation.
SERIAL OUTPUT COMMUNICATION (DEVICE
STATUS RETURN
DATA)
loaded. Meanwhile, the data is clocked out MSB first as the
new message data is clocked into the SI pin. The first 16 bits
of data clocking out of the SO, and following a
is dependant upon the previously written SPI word (SOA1
and SOA0 defined in the last SPI initialization word).
representative of the initial message bits clocked into the SI
pin since the
feature is useful for daisy chaining devices.
transition of logic [0] to logic [1]. If the message length is
valid, the data is latched into the appropriate registers. A valid
message length is a multiple of 16 bits. At this time, the SO
pin is tri-stated and the fault status register is now able to
accept new fault status information.
the Initialization-selected register data at the time that the
is pulled to a logic [0] during SPI communication and / or for
the period of time since the last valid SPI communication,
with the following exceptions:
SERIAL OUTPUT BIT ASSIGNMENT
from the most recent initialization command SOA[1:0] (refer
to
follow.
the fault is removed.
reflects Normal mode (NM).
Table
Same description as OUT1.
This register is reserved for test and is not available with
When the
Any bits clocked out of the SO pin after the first 16 will be
A valid message length is determined following a
The output status register correctly reflects the status of
•The previous SPI communication was determined to be
•Battery transients below 6.0 V, resulting in an under-
The contents of bits OD15 : OD0 depend on bits D1: D0
The register bits are reset by a read operation and also if
Table 11
invalid. In this case, the status will be reported as
though the invalid SPI communication never occurred.
voltage shutdown of the outputs, may result in incorrect
data loaded into the SPI register, except the UVF fault
reporting (OD13).
8, page 29), as explained in the paragraphs that
summarizes the SO register content. Bit OD10
CS
CS
pin is pulled low, the output register is
pin first transitioned to a logic [0]. This
LOGIC COMMANDS AND REGISTERS
FUNCTIONAL DEVICE OPERATION
CS
MC10XS3535
transition,
CS
CS
31