MC10XS3412DHFK Freescale Semiconductor, MC10XS3412DHFK Datasheet - Page 28

• Manufacturer Part Number: MC10XS3412DHFK
• Description: Power Switch ICs - Power Distribution Eswitch Gen3 1012
• Manufacturer: Freescale Semiconductor

Specifications of MC10XS3412DHFK

• Rohs: yes
• Number Of Outputs: 4
• Operating Supply Voltage: 6 V to 20 V
• Supply Current (max): 20 mA
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: PQFN-24
• Minimum Operating Temperature: - 40 C

SLEEP MODE
battery voltage (VPWR) prior to any I/O transitions. This is
also the state of the device when the WAKE and
IN_ON[0:3] are logic [0]. In the Sleep mode, the output and
all unused internal circuitry, such as the internal regulator, are
off to minimize draw current. In addition, all SPI-configurable
features of the device are as if set to logic [0].
NORMAL MODE
the outputs HS[0:3] are under control, as defined by hson
signal:
hson[x] = ( ( (IN[x] and DIR_dis[x]) or On bit[x] ) and PWM_en
) or (On bit [x] and Duty_cycle[x] and PWM_en).
depends on fault_control signal, as defined below:
fault_control[x] = ( (IN_ON[x] and DIR_dis[x]) and PWM_en )
or (On bit [x]).
Programmable PWM module
PWM module if PWM_en and On bits are set to logic [1].
clock is the factor 2
(CLOCK_sel bit). The outputs HS[0:3] can be controlled in
the range of 5% to 98% with a resolution of 7 bits of duty cycle
(Table
28
10XS3412
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 7. Output PWM Resolution
The 10XS3412 is in Sleep mode when:
• V
• wake-up = 0,
• fail = X,
• fault = X.
This is the Default mode of the device after first applying
The 10XS3412 is in Normal mode when:
• V
• wake-up = 1,
• fail = 0,
• fault = 0.
In this mode, the NM bit is set to lfault_contrologic [1] and
In this mode and also in Fail-safe, the fault condition reset
The outputs HS[0:3] are controlled by the programmable
The clock frequency from IN0 input pin or from internal
On bit
PWR
PWR
7). The state of other IN pin is ignored.
0
1
1
1
1
1
and V
and V
Duty cycle
DD
DD
0000000
0000001
0000010
1111111
7
are within the normal voltage range,
are within the normal voltage range,
(128) of the output PWM frequency
X
n
PWM ((n+1)/128 duty cycle)
PWM (1/128 duty cycle)
PWM (2/128 duty cycle)
PWM (3/128 duty cycle)
Output state
fully ON
OFF
RST
and
delay (number of PWM clock rising edges) to improve overall
EMC behavior of the light module
order to report a clock failure in case of the frequency is out
a specified frequency range (from f
case of clock failure, no PWM feature is provided, the On bit
defines the outputs state and the CLOCK_fail bit reports [1].
Calibratable internal clock
corresponding to typical f
reference already available to the MCU, the 10XS3412
allows clock period setting within +/-10 percent of accuracy.
Calibrating the internal clock is initiated by defined word to
CALR register. The calibration pulse is provided by the MCU.
The pulse is sent on the
launched. At the moment, the
to [0] until from logic [0] to [1] determine the period of internal
clock with a multiplicative factor of 128.
range (from t
be ignored and the internal clock will be unaltered or reset to
default value (f
IN0 input, when CLOCK_sel is set to [1].
The timing includes seven programmable PWM switching
The clock frequency from IN0 is permanently monitored in
The internal clock can vary as much as +/-30 percent
Using the existing SPI inputs and the precision timing
In case of negative
The calibratable clock is used, instead of the clock from
Table 8. Output PWM Switching Delay
CS
SI
Delay bits
000
001
010
011
100
101
110
111
CSB(MIN)
CALR
PWM(0)
) if this was not calibrated before.
to t
CS
Analog Integrated Circuit Device Data
CS
CSB(MAX)
PWM(0)
pulse is outside a predefined time
pin after the SPI word is
clock duration
112 PWM clock periods
CS
16 PWM clock periods
32 PWM clock periods
48 PWM clock periods
64 PWM clock periods
80 PWM clock periods
96 PWM clock periods
SI command
Internal
output switching period.
ignored
pin transitions from logic [1]
), the calibration event will
Output delay
(Table
Freescale Semiconductor
IN0(LOW)
no delay
8).
to f
IN0(HIGH)
). In