HV9957K7-G Supertex, HV9957K7-G Datasheet - Page 16

• Manufacturer Part Number: HV9957K7-G
• Description: LED Lighting Drivers LED DRIVER 6 CHANNEL W/ FAULT PROTECTION
• Manufacturer: Supertex

Specifications of HV9957K7-G

• Product Category: LED Lighting Drivers
• Rohs: yes
• Input Voltage: 5 V
• Maximum Supply Current: 10 mA
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-24
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 3000

Suggested PCB Layout
Pinout
ground plane, increasing switching losses.
and frequency. Keep trace length short
the IC, do not directly connect
Keep high current traces short
ground plane to avoid creating
PGND pin to underside plate.
Charge and discharge loop
ground plane close to the IC.
increases parasitic capacitance to the
and keep away from sensitive nodes.
To avoid injecting noise into
Switching node with high AC voltage
High current, high frequency
to minimize trace resistance
ground paths seperate from
Wide traces for the switching node,
Connect boost grounds to
voltage differentials across
areas small and highly
coincident, minimizing
while providing low resistance,
(top view)
Charge path (SW on)
Discharge path (SW off)
Supertex inc.
radiated EMI.
ground plane
V
IN
(top layer)
PGND1
PGND2
COMP
1235 Bordeaux Drive, Sunnyvale, CA 94089
SW1
SW2
EN
L
BST
1
2
3
4
5
6
If sensitive circuitry adjacent
to high voltage switching node,
include a guard trace.
C
C
IN
C
24
BST
7
BST
D
BST
23
8
GND
GND
22
GND
9
16
R
PGND1
PGND2
COMP
10
CM1
21
SW1
SW2
EN
To Host
20
11
HV9957
R
19
12
ISET
R
R
R
FLT
Tel: [phone]
To provide unbroken ground plane
for good heatsinking, do not use
thermal relief on ground vias.
Other vias requiring a clearance
ring should be kept distant from
the HV9957.
SFM1
SFM2
Y
C
18
17
16
15
14
13
C
GND
DIM
DD
DD1
CH6
CH5
CH4
CH3
CH2
CH1
CH6
CH5
CH4
CH3
CH2
CH1
GND
GND
R
FBS2
Ground plane not shown.
or V
DD
www.supertex.com
R
FBS1
Five vias to ground plane for
good thermal and electrical
conductivity. If ground plane
is a middle layer, consider a
second exposed plane for
heatsinking on the opposite
side. Use no thermal relief.
DV
or R
DD
DIM
Minimize copper area
to keep parasitic
capacitance from
loading the crystal.
AV
HV9957
V
BST
DD