LED7708 STMicroelectronics, LED7708 Datasheet - Page 45

• Manufacturer Part Number: LED7708
• Description: LED Lighting Drivers 16 Ch 85mA LED 3.6 to 36V 250kHz
• Manufacturer: STMicroelectronics

Specifications of LED7708

• Rohs: yes

LED7708
8.8
8.8.1
condition. Four options can be chosen by acting on the DTS1:DTS0 bits of the DEVCFG0
register (see
To prevent false triggering, the LED short-circuit detection is masked if the output voltage is
out of regulation (i.e. the OVRS bit of the DEVCFG0 is low). Each channel detected as faulty
(open or shorted) sets the corresponding bit of the CHSTA register.
The fault management algorithm can operate only if the channels are active and at a
minimum (10 µs typ.) PWM on-time is required at the outputs in order to detect the faulty
condition. After the detection of a “probably open channel”, the device begins to ramp-up the
output voltage, but this operation cannot be performed if the involved channel is turned off
(no feedback information available). In this case, the algorithm should wait until the channel
is turned on again, leading to a delayed output voltage steering because of the dimming
function. This situation can induce excessive power dissipation on the other channels (high-
voltage drop for a long period). To prevent this, the LED7708 automatically forces the
“probably open channel” to remain on (regardless of its programmed status) until the
maximum output voltage has been reached (confirmation of open channel fault) or the
output current has been recovered. Once the algorithm has recognized the open condition,
the faulty channel is excluded from the regulation loop and the output voltage is quickly
decreased to the optimal value in order to avoid excessive power dissipation (only if the
OCAD bit is asserted). Therefore, the open channel/LED-short fault detection algorithm can
operate in a transparent way without the need to stop the dimming function.
Special function
Current generators gain adjust
The gain of the current generators can be varied by changing the ADJ5:ADJ0 bits of the
DEVCFG1 register (64 steps). Two selectable ranges are provided by asserting/clearing the
current gain range selector (CGRS) bit of the DEVCFG1 register. After POR, the current
gain is unitary and can be changed according to the following formulas:
Equation 17
Equation 18
Equation 19
Table
G
D
=
16).
ADJ5x2
5
+
Doc ID 022698 Rev 1
ADJ4x2
G
CGRS
G
CGRS
4
=
+
0
=
ADJ3x2
1
=
=
0.75
1
+
+
2
G
+
G
D
ADJ2x2
D
Recommended operating conditions
⋅
⋅
0.5
------- -
64
0.25
---------- -
64
2
+
ADJ1x2
+
ADJ0
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