74LVC2G00DP-G NXP Semiconductors, 74LVC2G00DP-G Datasheet - Page 7

• Manufacturer Part Number: 74LVC2G00DP-G
• Description: Logic Gates 3.3V DUAL 2-INPUT NAND GATE
• Manufacturer: NXP Semiconductors

Specifications of 74LVC2G00DP-G

• Product Category: Logic Gates
• Rohs: yes
• Product: NAND
• Logic Family: LVC
• Number Of Gates: 2
• Number Of Lines (input / Output): 2 / 1
• High Level Output Current: - 32 mA
• Low Level Output Current: 32 mA
• Propagation Delay Time: 2.2 ns
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 1.65 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-505
• Minimum Operating Temperature: - 40 C
• Number Of Input Lines: 2
• Number Of Output Lines: 1
• Factory Pack Quantity: 3000
• Part # Aliases: 74LVC2G00DP,125

NXP Semiconductors
11. Dynamic characteristics
Table 8.
Voltages are referenced to GND (ground 0 V); for test circuit see
[1]
[3]
12. Waveforms
74LVC2G00
Product data sheet
[2]
Symbol Parameter
t
C
pd
Fig 8.
PD
Typical values are measured at nominal V
t
C
P
f
f
C
V
N = number of inputs switching;
Σ(C
pd
i
o
D
CC
PD
= input frequency in MHz;
L
= output frequency in MHz;
is the same as t
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in V;
× V
propagation delay nA, nB to nY; see
power dissipation
capacitance
Measurement points are given in
V
Input (nA, nB) to output (nY) propagation delays
PD
OL
Dynamic characteristics
CC
× V
2
and V
× f
CC
o
2
) = sum of outputs.
OH
× f
PLH
i
are typical output voltage levels that occur with the output load.
× N + Σ(C
and t
PHL
Conditions
per gate; V
L
V
V
V
V
V
× V
CC
CC
CC
CC
CC
CC
nA, nB input
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V
= 3.0 V to 3.6 V
= 4.5 V to 5.5 V
nY output
2
× f
Table
I
CC
o
All information provided in this document is subject to legal disclaimers.
= GND to V
) where:
and at T
9.
GND
V
V
OH
OL
V
Figure 8
I
Rev. 11 — 22 June 2012
amb
CC
= 25 °C.
D
in μW).
V
M
V
[2]
[3]
M
t
PHL
Figure
Min
1.2
0.7
0.7
0.7
0.5
-
−40 °C to +85 °C
9.
Typ
3.5
2.3
3.0
2.2
1.8
14
001aae972
t
[1]
PLH
Max
8.6
4.8
5.6
4.3
3.3
-
Dual 2-input NAND gate
−40 °C to +125 °C Unit
74LVC2G00
Min
1.2
0.7
0.7
0.7
0.5
-
© NXP B.V. 2012. All rights reserved.
Max
10.8
6.0
7.0
5.4
4.2
-
ns
ns
ns
ns
ns
pF
7 of 20