TS52001-MQFNR Triune Systems, TS52001-MQFNR Datasheet - Page 9

• Manufacturer Part Number: TS52001-MQFNR
• Description: Battery Management IC Hi-Eff Li-ON Charger w/MPPT-Lite
• Manufacturer: Triune Systems

Specifications of TS52001-MQFNR

• Rohs: yes
• Battery Type: Li-Ion
• Output Voltage: 0.4 V
• Output Current: 1.5 A
• Operating Supply Voltage: 4 V to 7.2 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Package / Case: QFN-16
• Charge Safety Timers: Yes
• Mounting Style: SMD/SMT
• Product Type: Charge Management
• Factory Pack Quantity: 1000
• Temperature Monitoring: Yes

SERIAL INTERFACE
The TS52001 features an I
configuration control for termination voltages, charge currents, and charge timeouts. This configurability allows for optimum
charging conditions in a wide range of Li-Ion batteries. I
is detected, the associated status bit in the STATUS register is set and the nFLT pin is pulled low. Whenever a warning is
detected, the associated status bit in the STATUS register is set, but the nFLT pin is not pulled low. Reading of the STATUS
register resets the fault and warning status bits, and the nFLT pin is released after all fault status bits have been reset.
I
I
The TS52001 has a slave I
standard version 3.0.
I
positive supply through an external pull-up resistor. The devices communicating on this bus can drive the SDA line low or
release it to high impedance. The device that initiates the I
initiated by the master sending a Start condition, a high-to-low transition on SDA, while the SCL line is high. After the Start
condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/nW). After
receiving the valid address byte, the device responds with an acknowledge (ACK). An ACK is a low on SDA during the high of
the ACK related clock pulse. On the I
must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as Start or
Stop control commands. A low-to-high transition on SDA while the SCL input is high, indicates a Stop condition and is sent by
the master (see Figure 4).
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop conditions. Each
byte of eight bits is followed by one ACK bit. The SDA line must be released by the transmitter before the receiver can send an
ACK bit. The receiver that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable
low during the high pulse of the ACK-related clock period. When a slave receiver is addressed, it must generate an ACK after
each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. To
ensure proper operation, setup and hold times must be met. An end of data is signaled by the master receiver to the slave
transmitter by not generating an acknowledge after the last byte has been clocked out of the slave. This is done by the master
receiver by holding the SDA line high. The transmitter must then release the data line to enable the master to generate a Stop
condition.
2
2
2
C is a two-wire serial interface where the two lines are serial clock (SCL) and serial data (SDA). SDA must be connected to a
C SUBADDRESS DEFINITION
C BUS OPERATION
Specifications subject to change
2
C interface that supports standard and fast mode data rates, auto-sequencing, and is compliant to I
2
C slave interface which offers advanced control and diagnostic features. I
2
C bus, during each clock pulse only one data bit is transferred. The data on the SDA line
Figure 3: Sub-address in I
WWW.TRIUNESYSTEMS.COM
2
C operation also offers fault and warning indicators. Whenever a fault
2
C transaction becomes the master of the bus. Communication is
- 9 -
2
C Transmission
Copyright © 2011, Triune Systems, LLC
2
C operation offers
TS52001
Version 1.3
2
C