89H34H16G2ZCBL IDT, 89H34H16G2ZCBL Datasheet - Page 2
![no-image](/images/no-image-200.jpg)
89H34H16G2ZCBL
Manufacturer Part Number
89H34H16G2ZCBL
Description
Peripheral Drivers & Components - PCIs
Manufacturer
IDT
Datasheet
1.89H32T8G2ZCBLG.pdf
(39 pages)
Specifications of 89H34H16G2ZCBL
Part # Aliases
IDT89H34H16G2ZCBL
IDT 89HPES32T8G2 Data Sheet
– Supports PCI Express Power Budgeting Capability
– SerDes power savings
– ECRC support
– AER on all ports
– SECDED ECC protection on all internal RAMs
– End-to-end data path parity protection
– Checksum Serial EEPROM content protected
– Autonomous link reliability (preserves system operation in the
– Ability to generate an interrupt (INTx or MSI) on link up/down
– On-chip link activity and status outputs available for Port 0
– Per port link activity and status outputs available using
– SerDes test modes
– Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG
– Requires only two power supply voltages (1.0 V and 2.5 V)
– No power sequencing requirements
9 General Purpose I/O
Reliability, Availability and Serviceability (RAS)
Test and Debug
Power Supplies
Packaged in a 23mm x 23mm 484-ball Flip Chip BGA with
1mm ball spacing
• Supports low swing / half-swing SerDes operation
• SerDes optionally turned-off in D3hot
• SerDes associated with unused ports are turned-off
• SerDes associated with unused lanes are placed in a low
presence of faulty links)
transitions
(upstream port)
external I
Note that a 3.3V is preferred for V
power state
2
C I/O expander for all other ports
DD
I/O
2 of 39
Product Description
provides the most efficient fan-out solution for applications requiring
high throughput, low latency, and simple board layout with a minimum
number of board layers. It provides 32 GBps (256 Gbps) of aggregated,
full-duplex switching capacity through 32 integrated serial lanes, using
proven and robust IDT technology. Each lane provides 5 GT/s of band-
width in both directions and is fully compliant with PCI Express Base
Specification, Revision 2.0.
tecture. The PCI Express layer consists of SerDes, Physical, Data Link
and Transaction layers in compliance with PCI Express Base specifica-
tion Revision 2.0. The PES32T8G2 can operate either as a store and
forward or cut-through switch. It supports eight Traffic Classes (TCs)
and one Virtual Channel (VC) with sophisticated resource management
to enable efficient switching and I/O connectivity for servers, storage,
and embedded processors with limited connectivity.
Utilizing standard PCI Express interconnect, the PES32T8G2
The PES32T8G2 is based on a flexible and efficient layered archi-
November 28, 2011