89H34H16G2ZCBL IDT, 89H34H16G2ZCBL Datasheet - Page 15
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89H34H16G2ZCBL
Manufacturer Part Number
89H34H16G2ZCBL
Description
Peripheral Drivers & Components - PCIs
Manufacturer
IDT
Datasheet
1.89H32T8G2ZCBLG.pdf
(39 pages)
Specifications of 89H34H16G2ZCBL
Part # Aliases
IDT89H34H16G2ZCBL
IDT 89HPES32T8G2 Data Sheet
JTAG
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST_N
1.
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
2.
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
The values for this symbol were determined by calculation, not by testing.
Signal
JTAG_TRST_N
1
,
JTAG_TMS
JTAG_TDO
JTAG_TCK
JTAG_TDI
Thigh_16a,
Symbol
Tpw_16d
Tper_16a
Tlow_16a
Tdz_16c
Thld_16b
Tsu_16b
Tdo_16c
2
2
Tpw_16d
Table 12 JTAG AC Timing Characteristics
Figure 4 JTAG AC Timing Waveform
JTAG_TCK falling
JTAG_TCK rising
Reference
Tsu_16b
Tsu_16b
Thld_16b
Thld_16b
Thigh_16a
Edge
none
none
15 of 39
Min
50.0
10.0
25.0
2.4
1.0
—
—
Tlow_16a
Tlow_16a
Tdo_16c
Max
25.0
20
20
—
—
—
—
Tper_16a
Unit
ns
ns
ns
ns
ns
ns
ns
Tdz_16c
Reference
See Figure 4.
Diagram
Timing
November 28, 2011