89H48H12G3YCHLG IDT, 89H48H12G3YCHLG Datasheet - Page 4

• Manufacturer Part Number: 89H48H12G3YCHLG
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: IDT

Specifications of 89H48H12G3YCHLG

• Rohs: yes

SMBus Interface
to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug
I/O expander. Two pins make up the SMBus master interface: an SMBus clock pin and an SMBus data pin. Four pins make up the SMBus slave inter-
face: an SMBus clock pin and an SMBus data pin plus two address pins, SSMBADDR[2,1].
SMBus lines that connect to the serial EEPROM and I/O expander slaves. In the split configuration, the master and slave SMBuses operate as two
independent buses; thus, multi-master arbitration is not required.
Hot-Plug Interface
PES48H12G2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset
and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES48H12G2 generates an SMBus transaction to the I/O
expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on
the IOEXPINTN input pin (alternate function of GPIO) of the PES48H12G2. In response to an I/O expander interrupt, the PES48H12G2 generates an
SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Pin Description
pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
IDT 89HPES48H12G2 Data Sheet
The PES48H12G2 contains an SMBus master interface. This master interface allows the default configuration register values of the PES48H12G2
The switch’s SMBus master interface does not support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the
The PES48H12G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the
The PES48H12G2 provides 9 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin
The following tables list the functions of the pins provided on the PES48H12G2. Some of the functions listed may be multiplexed onto the same
As shown in Figure 3, the master and slave SMBuses may only be used in a split configuration.
Figure 3 Split SMBus Interface Configuration
Switch
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
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EEPROM
Processor
Serial
SMBus
Master
...
Expander
Hot-Plug
I/O
Devices
SMBus
Other
November 28, 2011