W65C21S6TPG-14 Western Design Center (WDC), W65C21S6TPG-14 Datasheet - Page 16

• Manufacturer Part Number: W65C21S6TPG-14
• Description: Peripheral Drivers & Components - PCIs Peripheral Interface Adapter
• Manufacturer: Western Design Center (WDC)

Specifications of W65C21S6TPG-14

• Rohs: yes
• Operating Supply Voltage: 1.8 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-40
• Input Voltage Range (max): 5.5 V
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 10
• Supply Current (max): - 100 mA

PERIPHERAL I/O PORTS (PA0-PA7, PB0-PB7)
The Peripheral A and Peripheral B I/O ports allow the microprocessor to interface to the input lines on a
peripheral device by writing data into the Peripheral Output Register. They also allow the processor to
interface with a peripheral device’s output lines by reading the data on the Peripheral Port input lines
directly onto the data bus and into the internal registers of the processor.
Each of the peripheral I/O lines can be programmed to act as an input or an output. This is accomplished
by setting a 1 in the corresponding bit in the Data Direction Register for those lines that are to act as
outputs. A 0 in a bit of the Data Direction Register causes the corresponding Peripheral I/O lines to act
as an input.
The buffers that drive the Peripheral A I/O lines each contain two active pull-up transistors and one active
pull-down transistor. The pull-up transistors are resistive in nature and therefore allow the output voltage
to go to VCC for logic 1. The pull down transistors can sink a full 3.2 mA, making these buffers capable
of driving two standard TTL loads.
In the input mode, the W65C21S input pull-up transistors are connected to the I/O pin and will supply
50uA minimum pull-up current while the W65C22N will pull up greater than -200uA to drive two standard
TTL loads.
When in the output mode Port A can drive with similar current as the Port B buffers and can be thought of
as push-pull buffers. If Port A is clamped below 2.0V for logic 1 or above .8V for logic 0 the data read
during a read operation may not correspond to the value wrote to the output registers.
This is a
difference between the Port A buffers and the Port B buffers and also is a difference with older versions of
the PIA.
The Peripheral B I/O port duplicates many of the functions of the Peripheral A port. The process of
programming these lines to act as an input or an output is similar to the Peripheral A port, as is the effect
of reading or writing this port. However, there are several characteristics of the buffers driving these lines
that affect their use in peripheral interfacing.
The Peripheral B I/O buffers are push-pull devices, i.e., the pull-up devices are switched OFF in the 0
state and ON for a logic 1. Since these pull-ups are active devices, the logic 1 voltage will go to the VDD
power supply level.
Another difference between the PA0-PA7 lines and the PBO-PB7 lines is that they have three-state
capability which allows them to enter a high impedance state when programmed to be used as input
lines. In addition, data on these lines will be read properly, when programmed as output lines, even if the
data signals fall below 2.0 volts for a “high” state or are above 0.8 volts for a “low” state. When
programmed as output, each line can drive at least two TTL load and may also be used as a source of
up to 3.0 mA at 1.5 volts to directly drive the base of a transistor switch, such as a Darlington pair.
Limiting resistors should be used on the W65C21S to prevent excessive current when clamping an output
on both PA and PB port buffers.
The W65C21N have built in limiting resistors on PB0-PB7 and PA0-PA7 isn’t designed for Darlington
drive currents. Because these outputs are designed to drive transistors directly, the output data is read
directly from the Peripheral Output Register for those lines programmed to act as inputs.
The final characteristic is the high-impedance input state which is a function of the Peripheral B push-pull
buffers. When the Peripheral B I/O lines are programmed to act as inputs, the output buffer enters the
high impedance state. All pins are read when in the input mode.
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