W65C21S6TPG-14 Western Design Center (WDC), W65C21S6TPG-14 Datasheet - Page 12

• Manufacturer Part Number: W65C21S6TPG-14
• Description: Peripheral Drivers & Components - PCIs Peripheral Interface Adapter
• Manufacturer: Western Design Center (WDC)

Specifications of W65C21S6TPG-14

• Rohs: yes
• Operating Supply Voltage: 1.8 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-40
• Input Voltage Range (max): 5.5 V
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 10
• Supply Current (max): - 100 mA

SIGNAL DESCRIPTION
The PIA interfaces to the 65xx and 68xx microprocessor families with a reset line, a PHI2 clock line, a
read/write line, two interrupt request lines, two register select lines, three chip select lines and an 8-bit
bidirectional data bus. The PIA interfaces to the peripheral devices with four interrupt/control lines and
two 8-bit bidirectional data buses. Figures 1 and 2 show the pin assignments for these interface signals
and Figure 4 shows the interface relationship of these signals as they pertain to the CPU and the
peripheral devices.
CHIP SELECT (CS0, CS1, CS2B)
The PIA is selected when CS0 and CS1 are high and CS2B is low. These three chip select lines are
normally connected to the processor address lines either directly or through external decoder circuits.
When the PIA is selected, data will be transferred between the data lines and PIA registers, and/or
peripheral interface lines as determined by the RWB, RS0 and RS1 lines and the contents of Control
Registers A and B.
CLOCK SIGNAL (PHI2)
The Phase 2 Clock Signal (PHI2) is the system clock that triggers all data transfers between the CPU and
the PIA. PHI2 is generated by the CPU and us therefore the synchronizing signal between the CPU and
the PIA.
DATA BUS (D0-D7)
The eight bidirectional data bus lines are used to transfer data between the W65C21 and the
microprocessor.
During a Read operation, the contents of the W65C21 internal Data Bus Buffer (DBB) are transferred to
the microprocessor via the Data Bus lines. During a Write operation, the Data Bus lines represent high
impedance inputs over which data is transferred from the microprocessor to the Data Input Register
(DIR). The Data Bus lines are in the high impedance state when the W65C21 is unselected.
INTERRUPT STATUS CONTROL – CA1, CA2 (Port A) and CB1, CB2 (Port B)
The two Interrupt Status Control lines for each Data Port are controlled by the Interrupt Status Control
logic (A and B). This logic interprets the contents of the corresponding Control Register (CRA and CRB),
allowing the Interrupt Status Control lines to perform various peripheral control functions.
PERIPHERAL DATA PORT A (PA0-PA7)
Peripheral Data Port A is an 8-line, bidirectional bus used for the transfer of data, control and status
information between the W65C21 and a peripheral device. Each data port bus line may be individually
programmed as either an input or output under control of the Data Direction Register (DDRA). Data flow
direction may be selected on a line-by-line basis with intermixed input and output lines within the same
port.
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