MR0A08BCSO35R Everspin Technologies, MR0A08BCSO35R Datasheet - Page 10

• Manufacturer Part Number: MR0A08BCSO35R
• Description: NVRAM 3.3V 1Mb (128Kx8) MRAM
• Manufacturer: Everspin Technologies

Specifications of MR0A08BCSO35R

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Size: 128 KB
• Organization: 128 K x 8
• Interface Type: Parallel
• Access Time: 35 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Operating Current: 20 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: SOIC-32
• Maximum Power Dissipation: 0.6 W
• Operating Temperature Range: - 40 C to + 85 C
• Operating Voltage: 3 V to 3.6 V

Everspin Technologies © 2011
Timing Specifications
1
2
3
All write cycle timings are referenced from the last valid address to the first transition address.
Parameter
Write cycle time
Address set-up time
Address valid to end of write (
Address valid to end of write (
Enable to end of write (
Enable to end of write (
Data valid to end of write
Data hold time
Write recovery time
All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in
steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted
low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the
same time or before W goes high, the output will remain in a high-impedance state.
W (WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
A (ADDRESS)
D (DATA IN)
2
G
G
high)
low)
G
G
3
Figure 3.5 Write Cycle Timing 2 (E Controlled)
Table 3.5 Write Cycle Timing 2 (E Controlled)
high)
low)
t
AVEL
t
AVEH
10
Symbol
t
t
t
t
t
t
t
t
t
t
t
AVAV
AVEL
AVEH
AVEH
ELEH
ELWH
ELEH
ELWH
DVEH
EHDX
EHAX
t
AVAV
Hi-Z
Min
35
0
18
20
15
15
10
0
12
t
t
ELEH
ELWH
Data Valid
t
DVEH
1
Max
-
-
-
-
-
-
-
-
-
MR0A08B Rev. 5, 12/2011
t
EHDX
MR0A08B
t
EHAX
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns