MR0A08BCSO35R Everspin Technologies, MR0A08BCSO35R Datasheet

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FEATURES • 3.3 Volt power supply • Fast 35 ns read/write cycle • SRAM compatible timing • Native non-volatility • Unlimited read & write endurance • Data always non-volatile for >20-years at temperature • Commercial and industrial temperatures • RoHS-Compliant TSOP2, BGA and SOIC packages BENEFITS • One memory replaces FLASH, SRAM, EEPROM and BBSRAM in system for simpler, more efficient design • Improves reliability by replacing battery-backed SRAM INTRODUCTION The MR0A08B is a 1,048,576-bit magnetoresistive random access memory (MRAM) device organized as 131,072 words of 8 bits. The MR0A08B offers SRAM compatible 35 ns read/write timing with un- limited endurance. Data is always non-volatile for greater than 20-years. Data is automatically protected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification. The MR0A08B is the ideal memory solution for applications that must permanently store and retrieve critical data and programs quickly. The MR0A08B is available in small footprint 400-mil, 44-lead plastic small-outline TSOP type-2 package mm, 48-pin ball grid array (BGA) package with 0.75 mm ball centers or a 32-lead SOIC package. These packages are compatible with similar low-power SRAM products and other non-volatile RAM prod- ucts. The MR0A08B provides highly reliable data storage over a wide range of temperatures. The product is of- fered with commercial temperature (0 to +70 °C) and industrial temperature (-40 to +85 °C). CONTENTS 1. DEVICE PIN ASSIGNMENT......................................................................... 2 ...

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DEVICE PIN ASSIGNMENT OUTPUT G ENABLE BUFFER 7 A[16:0] ADDRESS 10 BUFFER 17 CHIP E ENABLE BUFFER WRITE W ENABLE BUFFER Signal Name Function A Address Input E Chip Enable W Write Enable G Output Enable DQ Data I/O V Power Supply DD V ...

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DEVICE PIN ASSIGNMENT Figure 1.2 Pin Diagrams for Available Packages (Top View DQ0 10 ...

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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. Parameter Supply voltage 2 Voltage on any pin 2 Output current per pin Package power dissipation Temperature under bias MR0A08B (Commercial) MR0A08BC (Industrial) Storage Temperature Lead temperature during solder (3 minute max) Maximum magnetic field during write MR0A08B (All Temperatures) Maximum magnetic field during read or standby Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera- 1 tion should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. All voltages are referenced Power dissipation capability depends on package characteristics and use environment. 3 Everspin Technologies © 2011 Table 2.1 Absolute ...

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Electrical Specifications Parameter Power supply voltage Write inhibit voltage Input high voltage Input low voltage Temperature under bias MR0A08B (Commercial) MR0A08BC (Industrial) There startup time once (max 0 (max (min (min Power Up and Power Down Sequencing The MRAM is protected from write operations whenever V there is a startup time before read or write operations can start. This time allows memory power supplies to stabilize. ...

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Electrical Specifications Parameter Input leakage current Output leakage current Output low voltage ( mA +100 μA) OL Output high voltage ( mA -100 μA) OL Parameter AC active supply current - read modes ( mA max) OUT DD AC active supply current - write modes (V = max) DD MR0A08B (Commercial) MR0A08BC (Industrial) AC standby current (V = max other ...

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TIMING SPECIFICATIONS Parameter Address input capacitance Control input capacitance Input/Output capacitance f = 1.0 MHz 3 °C, periodically sampled rather than 100% tested Parameter Logic input timing measurement reference level Logic output timing measurement reference level Logic input pulse levels Input rise/fall time Output load for low and high impedance parameters Output load for all other timing parameters Output Everspin Technologies © 2011 Table 3.1 Capacitance Symbol Table 3.2 AC Measurement Conditions Figure 3.1 Output Load Test Low and ...

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Timing Specifications Read Mode Parameter Read cycle time Address access time Enable access time 2 Output enable access time Output hold from address change Enable low to output active 3 Output enable low to output active Enable high to output Hi-Z 3 Output enable high to output Hi high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be 1 minimized or eliminated during read or write cycles. Addresses valid before or at the same time E goes low. 2 This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage (ADDRESS) Q (DATA OUT) Note: Device is continuously selected (E≤V A (ADDRESS) E (CHIP ENABLE) ...

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Timing Specifications Parameter Write cycle time 2 Address set-up time G Address valid to end of write ( G Address valid to end of write ( G Write pulse width ( high) G Write pulse width ( low) Data valid to end of write Data hold time Write low to data Hi-Z 3 Write high to output active 3 Write recovery time All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus 1 contention conditions must be minimized or eliminated during read and write cycles goes low at the same time or after W goes low, the output will remain in a high impedance state. After has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. 2 This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any given 3 voltage or temperate, t (max) < t WLQZ A (ADDRESS) E (CHIP ...

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Timing Specifications Parameter Write cycle time 2 Address set-up time G Address valid to end of write ( G Address valid to end of write ( G Enable to end of write ( high) G Enable to end of write ( low) Data valid to end of write Data hold time Write recovery time All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus 1 contention conditions must be minimized or eliminated during read and write cycles goes low at the same time or after W goes low, the output will remain in a high impedance state. After has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address goes low at the same time or after W goes low, the output will remain in a high-impedance state goes high at the 3 same time or before W goes high, the output will remain in a high-impedance state. A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) D ...

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Timing Specifications Table 3.6 Write Cycle Timing 3 (Shortened t Parameter Write cycle time 2 Address set-up time G Address valid to end of write ( G Address valid to end of write ( Write pulse width Data valid to end of write Data hold time Enable recovery time Write recovery time 3 Write to enable recovery time 3 All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus 1 contention conditions must be minimized or eliminated during read and write cycles goes low at the same time or after W goes low, the output will remain in a high impedance state. After has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address goes low at the same time or after W goes low the output will remain in a high impedance state goes high at the same 3 time or before W goes high the output will remain in a high impedance state. E must be brought high each cycle. Table 3.6 Write ...

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ORDERING INFORMATION Part Number Description MR0A08BYS35 3.3 V 128Kx8 MRAM Commercial MR0A08BCYS35 3.3 V 128Kx8 MRAM Industrial MR0A08BYS35R 3.3 V 128Kx8 MRAM Commercial MR0A08BCYS35R 3.3 V 128Kx8 MRAM Industrial MR0A08BMA35 3.3 V 128Kx8 MRAM Commercial MR0A08BCMA35 3.3 V 128Kx8 MRAM MR0A08BMA35R 3.3 V 128Kx8 MRAM Commercial MR0A08BCMA35R 3.3 V 128Kx8 MRAM Industrial MR0A08BSO35 3.3 V 128Kx8 MRAM Commercial MR0A08BCSO35 3.3 V 128Kx8 MRAM Industrial 1 Preliminary Product: This product is classified as Preliminary until the completion of all qualification tests. The speci- 1 fications in this data sheet are intended to be final but are subject to change. Please check the Everspin web site www. everspin.com for the latest information on product status. Everspin Technologies ...

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MECHANICAL DRAWING 1. Dimensions and tolerances per ASME Y14.5M - 1994. 2. Dimensions in Millimeters. 3. Dimensions do not include mold protrusion. 4. Dimension does not include DAM bar protrusions. DAM Bar protrusion shall not cause the lead width to exceed 0.58. Everspin Technologies © 2011 Figure 5.1 TSOP2 Print Version Not To Scale 13 MR0A08B MR0A08B Rev. 5, 12/2011 ...

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Mechanical Drawings BOTTOM VIEW 1. Dimensions in Millimeters. 2. Dimensions and tolerances per ASME Y14.5M - 1994. 3. Maximum solder ball diameter measured parallel to DATUM A 4. DATUM A, the seating plane is determined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package. Everspin Technologies © 2009 Figure 5.2 FBGA TOP VIEW 0.41 0.31 Print Version Not To Scale 14 MR0A08B 0.32 0.22 SIDE VIEW MR0A08B Rev. 5, 12/2011 ...

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Mechanical Drawings Unit Min 20.574 1.00 - Max 20.878 1.50 inch - Min 0.810 0.04 - Max 0.822 0.06 Everspin Technologies © 2011 Figure 5.3 SOIC PIN Print Version Not ...

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... Everspin makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technologies assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or inci- dental damages. “ ...