72V291L15PF IDT, 72V291L15PF Datasheet - Page 14

• Manufacturer Part Number: 72V291L15PF
• Description: FIFO
• Manufacturer: IDT

Specifications of 72V291L15PF

• Part # Aliases: IDT72V291L15PF

PROGRAMMABLE ALMOST-FULL FLAG (PAF
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D - m) words are
written to the FIFO. The PAF will go LOW after (65,536-m) writes for the
IDT72V281 and (131,072-m) writes for the IDT72V291. The offset “m” is the
full offset value. The default setting for this value is stated in the footnote of
Table 1.
IDT72V281 and (131,073-m) writes for the IDT72V291, where m is the full
offset value. The default setting for this value is stated in the footnote of
Table 2.
and FWFT Mode), for the relevant timing information.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE
FIFO reaches the almost-empty condition. In IDT Standard mode, PAE will
go LOW when there are n words or less in the FIFO. The offset “n” is the
empty offset value. The default setting for this value is stated in the footnote
of Table 1.
the FIFO. The default setting for this value is stated in the footnote of Table 2.
IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO
65,536 x 9 and 131,072 x 9
In FWFT mode, the PAF will go LOW after (65,537-m) writes for the
See Figure 18, Programmable Almost-Full Flag Timing (IDT Standard
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
PAF is synchronous and updated on the rising edge of WCLK.
The Programmable Almost-Empty flag (PAE) will go LOW when the
In FWFT mode, the PAE will go LOW when there are n+1 words or less in
PAF
PAF
PAF
PAF)
PAE
PAE
PAE)
PAE
TM
14
dard and FWFT Mode), for the relevant timing information.
HALF-FULL FLAG (HF
FIFO beyond half-full sets HF LOW. The flag remains LOW until the
difference between the write and read pointers becomes less than or equal
to half of the total depth of the device; the rising RCLK edge that accom-
plishes this condition sets HF HIGH.
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 65,536
for the IDT72V281 and 131,072 for the IDT72V291.
HF will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 65,537 for
the IDT72V281 and 131,073 for the IDT72V291.
for the relevant timing information. Because HF is updated by both RCLK
and WCLK, it is considered asynchronous.
DATA OUTPUTS (Q
See Figure 19, Programmable Almost-Empty Flag Timing (IDT Stan-
PAE is synchronous and updated on the rising edge of RCLK.
This output indicates a half-full FIFO. The rising WCLK edge that fills the
In IDT Standard mode, if no reads are performed after reset (MRS or
In FWFT mode, if no reads are performed after reset (MRS or PRS),
See Figure 20, Half-Full Flag Timing (IDT Standard and FWFT Modes),
(Q
0
- Q
8
) are data outputs for 9-bit wide data.
HF
HF
HF
HF)
0
-Q
8
)
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