72V3644L10PF IDT, 72V3644L10PF Datasheet - Page 30

• Manufacturer Part Number: 72V3644L10PF
• Description: FIFO
• Manufacturer: IDT

Specifications of 72V3644L10PF

• Part # Aliases: IDT72V3644L10PF

NOTES:
1. t
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
NOTES:
1. t
2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. If Port B size is word or byte, t
NOTES:
1. t
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT72V3624, 512 for the IDT72V3634, 1,024 for the IDT72V3644.
4. If Port B size is word or byte, t
CLKA
CLKB
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
CLKB
CLKA
CLKA
CLKB
ENA
ENB
ENA
AEB
ENB
AEA
ENA
AFA
ENB
CLKB edge is less than t
CLKA edge is less than t
CLKB edge is less than t
SKEW2
SKEW2
SKEW2
is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising
X1 Words in FIFO1
X2 Words in FIFO2
[D-(Y1+1)] Words in FIFO1
t
t
ENS2
ENS2
SKEW2
SKEW2
SKEW2
t
ENS2
Figure 23. Timing for AEB
SKEW2
Figure 24. Timing for AEA
SKEW2
, then AEB may transition HIGH one CLKB cycle later than shown.
, then AEA may transition HIGH one CLKA cycle later than shown.
, then AFA may transition HIGH one CLKA cycle later than shown.
Figure 25. Timing for AFA
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
is referenced to the rising CLKB edge that reads the last word or byte of the long word, respectively.
t
t
t
ENH
SKEW2
ENH
t
SKEW2
t
t
ENH
PAF
(1)
(1)
AEB
AEB
AEB
AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)
AEA
AEA
AEA
AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)
AFA
AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)
AFA
AFA
1
1
t
ENS2
TM
WITH BUS-MATCHING
30
t
SKEW2
t
2
(D-Y1) Words in FIFO1
ENH
2
t
PAE
t
(1)
PAE
1
COMMERCIAL TEMPERATURE RANGE
(X2+1) Words in FIFO2
(X1+1) Words in FIFO1
t
t
ENS2
ENS2
2
t
PAF
t
t
ENH
ENH
t
t
PAE
PAE
4664 drw26
4664 drw27
4664 drw25