72V3640L15PF IDT, 72V3640L15PF Datasheet
72V3640L15PF
Specifications of 72V3640L15PF
Related parts for 72V3640L15PF
72V3640L15PF Summary of contents
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... TDO IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. ...
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... Each FIFO has a data input port (D which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the state of external control pins Input Width (IW), Output Width (OW), and Bus- Matching (BM) pin during the Master Reset cycle. ...
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... There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines ...
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... During Master Reset (MRS) the following events occur: the read and write pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode. The Partial Reset (PRS) also sets the read and write pointers to the first location of the memory ...
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... RT being LOW. Refer to Figure 11 and 12 for Retransmit Timing with normal latency. Refer to Figure 13 and 14 for Zero Latency Retransmit Timing. The device can be configured with different input and output bus widths as shown in Table 1. A Big-Endian/Little-Endian data word format is provided. This function is useful when data is written into the FIFO in long word format (x36/x18) and read TABLE 1 — ...
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... In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs. Output Ready FF/IR In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full. In the Full Flag/ O FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO Input Ready memory ...
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... Asynchronous I A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW Read Port will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode. (1) ASYW Asynchronous I A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW Write Port will select Asynchronous operation ...
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... IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 ABSOLUTE MAXIMUM RATINGS Symbol Rating (2) V Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
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... SKEW2 NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Industrial temperature range product for 7-5ns and 15ns speed grades are available as standard device. All other speed grades are available by special order. 3. Pulse widths less than minimum values are not allowed. ...
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... Clock to Asynchronous Programmable Almost-Empty Flag PAEA NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Pulse widths less than minimum values are not allowed. 3. Values guaranteed by design, not currently tested. 4. Paramaeters apply to the PBGA package only. ...
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... IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load for t = 10ns CLK Output Load for t = 6ns, 7 ...
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... This mode uses the Empty Flag (EF) to indicate whether or not there are any words present in the FIFO. It also uses the Full Flag function (FF) to indicate whether or not the FIFO has any free space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using the Read Enable (REN) and RCLK ...
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... FSEL0 & FSEL1. TM 36-BIT FIFO PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72V3640/ 72V3650/72V3660/72V3670/72V3680/72V3690 have internal registers for these offsets. There are eight default offset values selectable during Master Offsets n,m Reset ...
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... IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 TABLE 3 ⎯ STATUS FLAGS FOR IDT STANDARD MODE IDT72V3640 0 Number of ( Words in (n+1) to 512 FIFO 513 to (1,024-(m+1)) (1,024-m) to 1,023 1,024 IDT72V3670 0 (1) Number of ...
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... NOTES: 1. The programming method can only be selected at Master Reset. 2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected. 3. The programming sequence applies to both IDT Standard and FWFT modes. Figure 3. Programmable Flag Offset Programming Sequence TM 36-BIT FIFO ...
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... IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 1st Parallel Offset Write/Read Cycle D/Q35 D/Q19 D/Q17 EMPTY OFFSET REGISTER (PAE 2nd Parallel Offset Write/Read Cycle ...
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... The act of reading the offset registers employs a dedicated read offset register pointer. The contents of the offset registers can be read on the Q pins when LD is set LOW and REN is set LOW. For x36 output bus width, data are read via Q transition of RCLK. Upon the second LOW-to-HIGH transition of RCLK, data are read from the Full Offset Register ...
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... TM 36-BIT FIFO COMMERCIAL AND INDUSTRIAL For either IDT Standard mode or FWFT mode, updating of the PAE, HF and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is synchronized to RCLK, thus on the second rising edge of RCLK after RT is setup, the PAE flag will be updated asynchronous, thus the rising edge of RCLK that RT is setup will update HF ...
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... When the read port is configured for Asynchronous operation the device must be operating on IDT standard mode, FWFT mode is not permissible if the read port is Asynchronous. The Empty Flag (EF) operates in an Asynchronous manner, that is, the empty flag will be updated based on both a read operation and a write operation ...
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... BUS-MATCHING (BM, IW, OW) The pins BM, IW and OW are used to define the input and output bus widths. During Master Reset, the state of these pins is used to configure the device bus sizes. See Table 1 for control settings. All flags will operate on the word/byte size boundary as defined by the selection of bus width ...
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... FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are double register-buffered outputs. EMPTY FLAG ( EF/OR ) This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF) function is selected. When the FIFO is empty, EF will go LOW, inhibiting further read operations. When EF is HIGH, the FIFO is not empty. See Figure 8, Read Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for the relevant timing information ...
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... RCLK edge that accomplishes this condition sets HF HIGH. In IDT Standard mode reads are performed after reset (MRS or PRS), HF will go LOW after (D writes to the FIFO, where D = 1,024 for the TM ...
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... IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT ...
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... IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT: ...
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... IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 MRS t RSS REN t RSS WEN t RSS FWFT/SI t RSS LD t RSS ASYW, ASYR t RSS FSEL0, FSEL1 t RSS BM, OW RSS BE t RSS RM t RSS PFM ...
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... IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36 PRS t RSS REN t RSS WEN t RSS RT t RSS SEN EF/OR FF/IR PAE PAF 36-BIT FIFO FWFT = HIGH HIGH t RSF If FWFT = LOW LOW ...
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... WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus SKEW1 of WCLK and the rising edge of RCLK is less than HIGH. 3. First data word latency = SKEW1 RCLK REF. Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode) TM 36-BIT FIFO t CLK t CLKH t CLKL 2 t ...
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... IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 36-BIT FIFO COMMERCIAL AND INDUSTRIAL 28 TEMPERATURE RANGES OCTOBER 22, 2008 ...
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... IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 36-BIT FIFO COMMERCIAL AND INDUSTRIAL 29 TEMPERATURE RANGES OCTOBER 22, 2008 ...
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... No more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 1,024 for IDT72V3640, 2,048 for IDT72V3650, 4,096 for IDT72V3660, 8,192 for IDT72V3670, 16,384 for the IDT72V3680 and 32,768 for the IDT72V3690. ...
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... No more than words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the IDT72V3690. ...
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... No more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 1,024 for IDT72V3640, 2,048 for IDT72V3650, 4,096 for IDT72V3660, 8,192 for IDT72V3670, 16,384 for the IDT72V3680 and 32,768 for the IDT72V3690. ...
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... DS SI BIT 0 NOTE for the IDT72V3640 for the IDT72V3650 for the IDT72V3660 for the IDT72V3670 for the IDT72V3680 and for the IDT72V3690. Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) TM 36-BIT FIFO ...
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... In IDT Standard mode 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660 and 8,192 for the IDT72V3670, 16,384 for the IDT72V3680 and 32,768 for the IDT72V3690. In FWFT mode 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the IDT72V3690. ...
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... In IDT Standard Mode 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680 and 32,768 for the IDT72V3690. In FWFT Mode 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the IDT72V3690. ...
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... In IDT Standard mode maximum FIFO depth 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680 and 32,768 for the IDT72V3690 FWFT mode maximum FIFO depth 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the IDT72V3690. ...
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... RCLK REN Qn Last Word EF t SKEW WR t CYH t CYC NOTE LOW and WEN = LOW. Figure 24. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode) TM 36-BIT FIFO t t ENS ENH FFA t CYC 2 t REF t CYL t t ...
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... EFA Last Word in Output Register NOTE LOW and REN = LOW. 2. Asynchronous Read is available in IDT Standard Mode only. Figure 26. Synchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode) TM 36-BIT FIFO WFF t CYC t CYH t AA ...
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... CYH CYL FFA FF NOTES LOW, WEN = LOW, and REN = LOW. 2. Asynchronous Read is available in IDT Standard Mode only. Figure 28. Asynchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode) TM 36-BIT FIFO ...
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... Do not connect any output control signals directly together. 3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths. Figure 29. Block Diagram of 1,024 x 72, 2,048 x 72, 4,096 x 72, 8,192 x 72, 16,384 x 72 and 32,768 x 72 Width Expansion TM 36-BIT FIFO avoided by creating composite flags, that is, ANDing EF of every FIFO, and separately ANDing FF of every FIFO ...
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... IDT72V3650, 4,096 for the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680 and 32,768 for the IDT72V3690 with an 36-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary ...
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... IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 TCK TDI/ TMS TDO t 6 TRST t 5 SYSTEM INTERFACE PARAMETERS Parameter Symbol Test Conditions Data Output t = Max DO Data Output Hold t DOH (1) Data Input ...
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... Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72V3640/72V3650/ 72V3660/72V3670/72V3680/72V3690 incorporates the necessary tap con- troller and modified pad cells to implement the JTAG facility. Note that IDT provides appropriate Boundary Scan Description Language program files for these devices. TDO T ...
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... IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 Input = TMS NOTES: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. 2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS). ...
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... The Device Identification Register is a Read Only 32-bit register used to specify the manufacturer, part number and version of the processor to be determined through the TAP in response to the IDCODE instruction. IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is dropped in the 11-bit Manufacturer ID field. For the IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690, ...
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... SuperSync™ II FIFO 2,048 x 36 ⎯ 3.3V SuperSync™ II FIFO 4,096 x 36 ⎯ 3.3V SuperSync™ II FIFO 8,192 x 36 16,384 x 36 ⎯ 3.3V SuperSync™ II FIFO 32,768 x 36 ⎯ 3.3V SuperSync™ II FIFO 4667 drw 39 for Tech Support: 408-360-1753 email: FIFOhelp@idt.com ) CLK ...