72V2101L15PFI IDT, 72V2101L15PFI Datasheet - Page 22

• Manufacturer Part Number: 72V2101L15PFI
• Description: FIFO 256Kx9 SUPERSYNC FIFO, 3.3V
• Manufacturer: IDT

Specifications of 72V2101L15PFI

• Part # Aliases: IDT72V2101L15PFI

NOTE:
1. X = 17 for the IDT72V2101 and X = 18 for the IDT72V2111.
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup
3. OE = LOW
4. W
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
Q
WCLK
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
WCLK
RCLK
0
procedure. D = 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111.
SEN
WEN
REN
- Q
PAE
PAF
LD
1
OR
, W
SI
RT
HF
n
2
, W
t
ENS
3
= first, second and third words written to the FIFO after Master Reset.
W
x
TM
262,144 x 9, 524,288 x 9
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
ENH
BIT 0
t
t
LDS
t
ENS
DS
t
ENS
t
RTS
t
RTS
t
t
ENH
LDH
W
x+1
EMPTY OFFSET
t
t
REF
t
ENH
HF
t
SKEW2
Figure 12. Retransmit Timing (FWFT Mode)
1
2
t
PAF
1
t
A
t
BIT X
REF
22
(1)
t
ENS
W
BIT 0
1
(4)
2
t
A
t
PAE
FULL OFFSET
W
2
(4)
3
t
A
COMMERCIAL AND INDUSTRIAL
W
3
TEMPERATURE RANGES
(4)
t
BIT X
LDH
t
t
ENH
DH
(1)
4
t
A
W
4669 drw 16
4669 drw 15
4
t
ENH