72V2101L15PFI IDT, 72V2101L15PFI Datasheet - Page 10

• Manufacturer Part Number: 72V2101L15PFI
• Description: FIFO 256Kx9 SUPERSYNC FIFO, 3.3V
• Manufacturer: IDT

Specifications of 72V2101L15PFI

• Part # Aliases: IDT72V2101L15PFI

NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
TM
LD
0
0
0
X
1
1
1
262,144 x 9, 524,288 x 9
WEN
X
0
1
1
1
0
1
REN
X
1
0
1
1
0
1
Figure 4. Programmable Flag Offset Programming Sequence
SEN
1
1
X
X
X
1
0
WCLK
X
X
X
X
RCLK
10
X
X
X
X
X
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (Mid-Byte)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (Mid-Byte)
Full Offset (MSB)
Serial shift into registers:
36 bits for the 72V2101
38 bits for the 72V2111
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with FUll Offset (MSB)
No Operation
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (Mid-Byte)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (Mid-Byte)
Full Offset (MSB)
Write Memory
Read Memory
No Operation
IDT72V2101
IDT72V2111
COMMERCIAL AND INDUSTRIAL
4669 drw 07
TEMPERATURE RANGES