74ACTQ573SC_Q Fairchild Semiconductor, 74ACTQ573SC_Q Datasheet - Page 2

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74ACTQ573SC_Q

Manufacturer Part Number
74ACTQ573SC_Q
Description
Latches Octal Latch
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of 74ACTQ573SC_Q

Number Of Circuits
8
Logic Type
Latch
Logic Family
74ACT
Polarity
Non-Inverting
Number Of Output Lines
3
High Level Output Current
- 24 mA
Propagation Delay Time
7.5 ns at 5 V
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Package / Case
SOIC-20
Mounting Style
SMD/SMT
Number Of Input Lines
8
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
Logic Symbol
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
IEEE/IEC
2
Functional Description
The ACQ/ACTQ573 contains eight D-type latches with
3-STATE output buffers. When the Latch Enable (LE)
input is HIGH, data on the D
In this condition the latches are transparent, i.e., a latch
output will change state each time its D-type input
changes. When LE is LOW the latches store the informa-
tion that was present on the D-type inputs at setup time
preceding the HIGH-to-LOW transition of LE. The
3-STATE buffers are controlled by the Output Enable
(OE) input. When OE is LOW, the buffers are enabled.
When OE is HIGH the buffers are in the high impedance
mode but this does not interfere with entering new data
into the latches.
Truth Table
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O
Latch Enable
0
= Previous O
OE
H
L
L
L
Inputs
0
LE
before HIGH-to-LOW transition of
H
H
X
L
n
inputs enters the latches.
D
H
X
X
L
Outputs
www.fairchildsemi.com
O
O
H
Z
L
n
0

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