74ACT74SC Fairchild Semiconductor, 74ACT74SC Datasheet

IC F/F DL D-TYPE POS EDGE 14SOIC

74ACT74SC

Manufacturer Part Number
74ACT74SC
Description
IC F/F DL D-TYPE POS EDGE 14SOIC
Manufacturer
Fairchild Semiconductor
Series
74ACTr
Type
D-Typer
Datasheet

Specifications of 74ACT74SC

Function
Set(Preset) and Reset
Output Type
Differential
Number Of Elements
2
Number Of Bits Per Element
1
Frequency - Clock
210MHz
Delay Time - Propagation
7.5ns
Trigger Type
Positive Edge
Current - Output High, Low
24mA, 24mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Number Of Circuits
2
Logic Family
74ACT
Logic Type
D-Type Edge Triggered Flip-Flop
Polarity
Inverting/Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
11 ns
High Level Output Current
- 24 mA
Low Level Output Current
24 mA
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
4.5 V
Flip-flop Type
D
Propagation Delay
5.5ns
Frequency
210MHz
Output Current
24mA
Ic Output Type
Differential / Complementary
Supply Voltage Range
4.5V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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© 1999 Fairchild Semiconductor Corporation
74AC74 • 74ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The AC/ACT74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at
a voltage level of the clock pulse and is not directly related
to the transition time of the positive-going pulse. After the
Clock Pulse input threshold voltage has been passed, the
Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
Asynchronous Inputs:
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
FACT
Order Number
74AC74SC
74AC74SJ
74AC74MTC
74AC74PC
74ACT74SC
74ACT74SJ
74ACT74MTC
74ACT74PC
LOW input to S
LOW input to C
Clear and Set are independent of clock
Simultaneous LOW on C
HIGH
is a trademark of Fairchild Semiconductor Corporation.
D
D
Package Number
(Set) sets Q to HIGH level
(Clear) sets Q to LOW level
MTC14
MTC14
M14A
M14D
M14A
M14D
N14A
N14A
D
and S
D
makes both Q and Q
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
DS009920
Features
Pin Descriptions
I
Output source/sink 24 mA
ACT74 has TTL-compatible inputs
CC
reduced by 50%
D
CP
C
S
Q
Package Description
1
D1
D1
1
, D
, Q
1
, C
, S
, CP
Pin Names
2
1
D2
D2
, Q
2
2
, Q
2
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
November 1988
Revised November 1999
Description
www.fairchildsemi.com

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74ACT74SC Summary of contents

Page 1

... MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACT74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body 74ACT74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ...

Page 2

Logic Symbols Truth Table (Each Half HIGH Voltage Level L LOW Voltage Level  X Immaterial LOW-to-HIGH Clock Transition Previous Q (Q) before LOW-to-HIGH Transition of Clock 0 0 Logic Diagram Please note that this ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. 0. Input Voltage ( Output Diode Current ( ...

Page 4

DC Electrical Characteristics for ACT V Symbol Parameter V Minimum HIGH Level IH Input Voltage V Maximum LOW Level IL Output Voltage V Minimum HIGH Level OH Output Voltage V Maximum LOW Level OL Output Voltage I Maximum Input IN ...

Page 5

AC Operating Requirements for AC Symbol Parameter t Set-up Time, HIGH or LOW Hold Time, HIGH or LOW ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body www.fairchildsemi.com Package Number M14A 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide www.fairchildsemi.com Package Number MTC14 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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