74ACT573PC_Q Fairchild Semiconductor, 74ACT573PC_Q Datasheet

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74ACT573PC_Q

Manufacturer Part Number
74ACT573PC_Q
Description
Latches Octal Latch
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of 74ACT573PC_Q

Number Of Circuits
8
Logic Type
Latch
Logic Family
74ACT
Polarity
Non-Inverting
Number Of Output Lines
3
High Level Output Current
- 24 mA
Propagation Delay Time
10.5 ns at 5 V
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Package / Case
PDIP-20
Mounting Style
Through Hole
Number Of Input Lines
8
©1988 Fairchild Semiconductor Corporation
74AC573, 74ACT573 Rev. 1.6.0
74AC573, 74ACT573
Octal Latch with 3-STATE Outputs
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
74AC573SC
74AC573SJ
74AC573MTC
74ACT573SC
74ACT573SJ
74ACT573MTC
74ACT573PC
I
Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
Useful as input or output port for microprocessors
Functionally identical to 74AC373 and 74ACT373
3-STATE outputs for bus interfacing
Outputs source/sink 24mA
74ACT573 has TTL-compatible inputs
CC
Order Number
All packages are lead free per JEDEC: J-STD-020B standard.
and I
OZ
reduced by 50%
Package
Number
MTC20
MTC20
M20B
M20D
M20B
M20D
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
General Description
The 74AC573 and 74ACT573 are high-speed octal
latches with buffered common Latch Enable (LE) and
buffered common Output Enable (OE) inputs.
The 74AC573 and 74ACT573 are functionally identical
to the 74AC373 and 74ACT373 but with inputs and
outputs on opposite sides.
Package Description
January 2008
www.fairchildsemi.com

Related parts for 74ACT573PC_Q

74ACT573PC_Q Summary of contents

Page 1

... N20A Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6.0 General Description The 74AC573 and 74ACT573 are high-speed octal latches with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs ...

Page 2

... Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6.0 Logic Symbols Truth Table ...

Page 3

... Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6.0 3 www.fairchildsemi.com ...

Page 4

... V Output Voltage O T Operating Temperature Minimum Input Edge Rate, AC Devices: V from 30 Minimum Input Edge Rate, ACT Devices: V from 0.8V to 2.0V ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6.0 Parameter Parameter , V @ 3.3V, 4.5V, 5. 4.5V, 5. Rating –0.5V to +7.0V –20mA +20mA –0. 0.5V CC – ...

Page 5

... All outputs loaded; thresholds on input associated with output under test and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5. Maximum test duration 2.0ms, one output loaded at a time. ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6 (V) Conditions Typ ...

Page 6

... Minimum Dynamic OLD (5) Output Current I OHD I Maximum Quiescent CC Supply Current Notes: 4. All outputs loaded; thresholds on input associated with output under test. 5. Maximum test duration 2.0ms, one output loaded at a time. ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6 (V) Conditions Typ. CC 4.5 V 0.1V or 1.5 ...

Page 7

... Parameter t Setup Time, HIGH or LOW Hold Time, HIGH or LOW Pulse Width, HIGH W Note: 7. Voltage range 5.0 is 5.0V ± 0.5V. Voltage range 3.3 is 3.3V ± 0.3V. ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6.0 T +25° 50pF L (6) V (V) Min. Typ. Max. CC 3.3 0.5 8.5 10 ...

Page 8

... Hold Time, HIGH or LOW Pulse Width, HIGH W Note: 9. Voltage range 5.0 is 5.0V ± 0.5V. Capacitance Symbol Parameter C Input Capacitance IN C Power Dissipation Capacitance PD AC ACT ©1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6.0 T +25° 50pF L (8) V (V) Min. Typ. Max. CC 5.0 2.5 6.0 10.5 5.0 3.0 6 ...

Page 9

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 10

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 11

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 12

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 13

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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