74ACT573MTC_Q Fairchild Semiconductor, 74ACT573MTC_Q Datasheet - Page 2

• Manufacturer Part Number: 74ACT573MTC_Q
• Description: Latches Octal Latch
• Manufacturer: Fairchild Semiconductor

Specifications of 74ACT573MTC_Q

• Number Of Circuits: 8
• Logic Type: Latch
• Logic Family: 74ACT
• Polarity: Non-Inverting
• Number Of Output Lines: 3
• High Level Output Current: - 24 mA
• Propagation Delay Time: 10.5 ns at 5 V
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: TSSOP-20
• Mounting Style: SMD/SMT
• Number Of Input Lines: 8

©1988 Fairchild Semiconductor Corporation
74AC573, 74ACT573 Rev. 1.6.0
Connection Diagram
Pin Description
Functional Description
The 74AC573 and 74ACT573 contain eight D-type
latches with 3-STATE output buffers. When the Latch
Enable (LE) input is HIGH, data on the D
the latches. In this condition the latches are transparent,
i.e., a latch output will change state each time its D-type
input changes. When LE is LOW the latches store the
information that was present on the D-type inputs a
setup time preceding the HIGH-to-LOW transition of LE.
The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are
enabled. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
D
LE
OE
O
0
0
Pin Names
–D
–O
7
7
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
Description
n
inputs enters
2
Logic Symbols
Truth Table
H
L
Z
X
O
Latch Enable
0
LOW Voltage
High Impedance
OE
Immaterial
HIGH Voltage
H
L
L
L
Previous O
Inputs
LE
0
H
H
X
L
before HIGH-to-LOW transition of
IEEE/IEC
D
H
X
X
L
Outputs
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O
O
H
L
Z
n
0