TDA8594SD/N1S,112 NXP Semiconductors, TDA8594SD/N1S,112 Datasheet - Page 5

• Manufacturer Part Number: TDA8594SD/N1S,112
• Description: Audio Amplifiers GEN PURP 75W 45dB
• Manufacturer: NXP Semiconductors

Specifications of TDA8594SD/N1S,112

• Rohs: yes
• Product: General Purpose Audio Amplifiers
• Output Type: Fixed
• Output Power: 75 W
• Maximum Power Dissipation: 80 W
• Mounting Style: SMD/SMT
• Package / Case: SOT-878-1
• Common Mode Rejection Ratio (min): 45 dB
• Factory Pack Quantity: 19

NXP Semiconductors
7. Functional description
TDA8594
Product data sheet
7.1 Input stage
Table 3.
To keep the output pins on the front side, special reverse bending is applied.
The TDA8594 is a complementary quad BTL audio power amplifier made in BCDMOS
technology. It contains four independent amplifiers in BTL configuration (see
Through the I
programmable and the information to be shown on the two diagnostic pins can be
selected. The status of each amplifier (output offset, load or no load, short-circuit or
speaker incorrectly connected) can be read separately. The TDA8594 is protected against
overvoltage, short-circuit, over-temperature, open ground and open V
Three different I
ADSEL pin. If the ADSEL pin is short-circuit to ground, the TDA8594 operates in legacy
mode. In this mode, no I
two-level (Standby mode and On mode) to a three-level pin (Standby mode, On mode and
mute).
The input stage is a high-impedance pseudo-differential input stage. The negative inputs
of the four channels are combined on the ACGND pin. For the best performance on
supply voltage ripple rejection and pop noise, the capacitor connected to the ACGND pin
must be four times the value of the input capacitor (or as close to the value as possible).
Symbol
OUT1
PGND1
OUT1+
SVR
IN1
IN2
SGND
IN4
IN3
ACGND
OUT3+
PGND3
OUT3
V
OUT4+
SCL
OUT4
PGND4
SDA
TAB
P1
Pin description
Pin
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
2
C-bus, the diagnostic functions of temperature level and clip level are fully
All information provided in this document is subject to legal disclaimers.
2
C-bus addresses are selected with an external resistor connected to the
negative channel 1 output
power ground channel 1
positive channel 1 output
half supply filter capacitor
channel 1 input
channel 2 input
signal ground
channel 4 input
channel 3 input
AC ground input
positive channel 3 output
power ground channel 3
positive channel 4 output
I
power ground channel 4
I
Description
negative channel 3 output
supply voltage 1
negative channel 4 output
heatsink connection, must be connected to ground
2
2
Rev. 4 — 26 February 2013
C-bus clock input
C-bus data input/output
2
C-bus is needed and the function of the STB pin will change from
…continued
I
2
C-bus controlled 4  50 W power amplifier
P
TDA8594
© NXP B.V. 2013. All rights reserved.
connections.
Figure
1).
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