TDA8595TH/N2S,112 NXP Semiconductors, TDA8595TH/N2S,112 Datasheet - Page 30

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TDA8595TH/N2S,112

Manufacturer Part Number
TDA8595TH/N2S,112
Description
Audio Amplifiers GEN PURP 64W 45dB
Manufacturer
NXP Semiconductors
Datasheet

Specifications of TDA8595TH/N2S,112

Rohs
yes
Product
General Purpose Audio Amplifiers
Output Type
Fixed
Output Power
64 W
Maximum Power Dissipation
80 W
Mounting Style
SMD/SMT
Package / Case
HSOP-36
Common Mode Rejection Ratio (min)
45 dB
Factory Pack Quantity
30
NXP Semiconductors
Table 17.
Refer to test circuit (see
specified. Tested at T
TDA8595
Product data sheet
Symbol
t
t
t
t
t
t
t
I
V
V
V
amp_on
off
d(mute-on)
d(soft_mute)
d(fast_mute)
(start-Vo(off))
(start-SVRoff)
2
C-bus interface
IL
IH
OL
Characteristics
Parameter
amplifier on time
amplifier switch-off time
mute to on delay time
soft mute delay time
fast mute delay time
engine start to output off
time
engine start to SVR off time V
LOW-level input voltage
HIGH-level input voltage
LOW-level output voltage
[4]
amb
Figure
= 25
…continued
30) at V
C; guaranteed for T
P
= V
All information provided in this document is subject to legal disclaimers.
P1
Conditions
time from amplifier mute to
amplifier on; 90 % of output
signal; I
time to DC output voltage < 0.1 V;
I
from 10 % to 90 % of output
signal; IB2[D1/D2] = 1 to 0;
V
from 90 % to 10 % of output
signal; V
IB2[D1/D2] = 0 to 1; see
from 90 % to 10 % of output
signal; V
see
V
see
V
pins SCL and SDA
pins SCL and SDA
pin SDA; I
2
= V
C-bus mode; I
i
P
P
SVR
I
with I
no DC load (IB1[D1] = 0);
low pop disabled (IB2[D3] = 1);
see
I
with I
DC load active (IB1[D1] = 1);
low pop disabled (IB2[D3] = 1);
see
I
with I
DC load active (IB1[D1] = 1);
low pop enabled (IB2[D3] = 0);
see
legacy mode;
with I
V
see
low pop disabled (IB2[D3] = 1);
with I
see
low pop enabled (IB2[D3] = 0);
with I
see
= 50 mV; see
2
2
2
from 14.4 V to 7 V; V
from 14.4 V to 7 V;
C-bus mode;
C-bus mode;
C-bus mode;
STB
Rev. 4 — 26 February 2013
Figure 7
Figure 9
P2
amb
< 2 V; see
Figure 4
Figure 5
Figure 6
Figure 7
Figure 5
Figure 6
= 14.4 V; R
LO
LO
LO
LO
LO
LO
LO
= 7 V; R
i
STB
=
= 50 mV;
L
= 10 A  +30 ms;
= 10 A  +35 ms;
= 10 A  +30 ms;
= 10 A  +20 ms;
= 10 A  +0 ms;
= 10 A  +0 ms;
= 0 A
= 5 mA
40
from 8 V to 1.3 V;
ADSEL
LO
C to +105
Figure 7
Figure 9
L
= 0 A
= 4
= 0 ;
o
Figure 7
< 0.5 V;
; f = 1 kHz; R
I
2
C.
C-bus controlled 4  45 W power amplifier
[3]
[3]
S
= 0
Min
360
565
710
510
120
140
-
-
-
-
-
-
2.3
-
; normal mode; unless otherwise
Typ
520
695
890
720
245
280
20
20
0.1
0.1
40
-
-
TDA8595
© NXP B.V. 2013. All rights reserved.
Max
870
1015
1270
1120
530
620
40
40
1
1
75
0.4
1.5
5.5
ms
ms
ms
ms
ms
ms
ms
ms
ms
Unit
ms
ms
V
V
V
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