TJA1022T,118 NXP Semiconductors, TJA1022T,118 Datasheet - Page 9

• Manufacturer Part Number: TJA1022T,118
• Description: LIN Transceivers DUAL LIN 5-18V
• Manufacturer: NXP Semiconductors

Specifications of TJA1022T,118

• Rohs: yes
• Operating Supply Voltage: 5 V to 18 V
• Supply Current: 10 mA
• Package / Case: SO-14
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 2500

NXP Semiconductors
TJA1022
Product data sheet
7.6 Fail-safe features
If the voltage on pin V
the TJA1022 switches to Reset mode (i.e. all output drivers are disabled and all inputs are
ignored). The TJA1022 switches to Sleep mode if V
Pin TXDx is pulled down to ground in order to force a predefined level on the transmit data
input if the pin is disconnected.
Pin SLPx_N is pulled down to ground to ensure the transceiver is forced to Sleep x mode
if SLPx_N is disconnected.
Pins RXD1 and RXD2 are set floating if V
The current in the transmitter output stage is limited in order to protect the transmitter
against short circuits to pins V
A loss of power (pins V
microcontroller. No reverse current will flow from the bus lines into the LINx pins. The
current path from V
The TJA1022 can be disconnected from the power supply without influencing the LIN
busses.
The output drivers on pins LIN1 and LIN2 are protected against overtemperature
conditions. If the junction temperature exceeds the shutdown junction temperature, T
the thermal protection circuit disables the output drivers. The drivers are enabled again
when the junction temperature falls below T
The initial TXD dominant check prevents the bus being driven to a permanent dominant
state (blocking all network communications) if pin TXDx is forced permanently LOW by a
hardware and/or software application failure. The input level on TXDx is checked after a
transition to Normal mode. If TXDx is LOW, the transmit path will remain disabled and will
only be enabled when TXDx goes HIGH.
Once the transmitter has been enabled, a TXD dominant time-out timer is started every
time pin TXDx goes LOW. If the LOW state on pin TXDx persists for longer than the
TXD dominant time-out time (t
line to recessive state. The TXD dominant time-out timer is reset when pin TXDx goes
HIGH.
All information provided in this document is subject to legal disclaimers.
BAT
BAT
BAT
to LINx via the integrated LIN slave termination resistors remains.
Rev. 1 — 30 March 2012
drops below the LOW-level power-on reset threshold, V
and GND) has no impact on the bus lines or on the
BAT
to(dom)TXD
or GND.
), the transmitter is disabled, releasing the bus
BAT
j(sd)
is disconnected.
and pin TXDx is HIGH.
Dual LIN 2.2/SAE J2602 transceiver
BAT
> V
th(POR)H
.
TJA1022
© NXP B.V. 2012. All rights reserved.
th(POR)L
9 of 26
j(sd)
,
,