XRT91L32ES Exar, XRT91L32ES Datasheet - Page 4

• Manufacturer Part Number: XRT91L32ES
• Description: LIN Transceivers SONET SDH 8 bit TRANCEIVER
• Manufacturer: Exar

Specifications of XRT91L32ES

• Product Category: LIN Transceivers
• Rohs: yes

XRT91L32
REV. 1.0.3
GENERAL DESCRIPTION .................................................................................................1
T
PIN DESCRIPTIONS ..........................................................................................................4
1.0 FUNCTIONAL DESCRIPTION .............................................................................................................11
2.0 RECEIVE SECTION .............................................................................................................................12
3.0 TRANSMIT SECTION ..........................................................................................................................21
ABLE OF
APPLICATIONS ...........................................................................................................................................1
FEATURES
H
T
R
P
.....................................................................................................................................................................4
RANSMITTER
OWER AND
ORDERING INFORMATION.....................................................................................................................3
ARDWARE
ECEIVER
1.1 STS-12/STM-4 AND STS-3/STM-1 MODE OF OPERATION ......................................................................... 11
1.2 CLOCK INPUT REFERENCE FOR CLOCK MULTIPLIER (SYNTHESIZER) UNIT ...................................... 11
1.3 DATA LATENCY ............................................................................................................................................. 11
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 12
2.2 RECIEVE SERIAL DATA INPUT TIMING ...................................................................................................... 13
2.3 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 14
2.4 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 16
2.5 LOSS OF SIGNAL .......................................................................................................................................... 16
2.6 SONET FRAME BOUNDARY DETECTION AND BYTE ALIGNMENT RECOVERY .................................... 17
2.7 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 17
2.8 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 18
2.9 DISABLE PARALLEL RECEIVE DATA OUTPUT UPON LOS ..................................................................... 18
2.10 RECEIVE PARALLEL DATA OUTPUT TIMING .......................................................................................... 19
3.1 TRANSMIT PARALLEL INPUT INTERFACE ................................................................................................. 21
3.2 TRANSMIT PARALLEL DATA INPUT TIMING .............................................................................................. 22
3.3 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 23
3.4 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 23
3.5 LOOP TIMING AND CLOCK CONTROL ........................................................................................................ 24
F
F
T
T
F
F
T
T
T
T
F
F
F
F
F
F
T
T
T
F
F
T
T
F
T
T
IGURE
IGURE
ABLE
ABLE
IGURE
IGURE
ABLE
ABLE
ABLE
ABLE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
ABLE
ABLE
ABLE
IGURE
IGURE
ABLE
ABLE
IGURE
ABLE
ABLE
2.3.1 INTERNAL CLOCK AND DATA RECOVERY BYPASS ............................................................................................ 15
1: CMU R
2: D
3: R
4: R
5: C
6: C
7: R
8: R
9: PECL
10: T
11: T
12: C
13: L
1. B
2. 100 QFP P
3. R
4. R
5. I
6. E
7. LOS D
8. S
9. R
10. R
11. T
12. T
13. S
C
......................................................................................................................................................2
S
ONTENTS
C
ECTION
G
ATA INGRESS TO DATA EGRESS LATENCY
ECEIVE
ECEIVE
LOCK
LOCK AND
NTERNAL
ECEIVE
ECEIVE
ONTROL
OOP
LOCK
ECEIVE
ECEIVE
XTERNAL
IMPLIFIED
ECEIVE
RANSMIT
RANSMIT
LOCK
S
ROUND
RANSMIT
RANSMIT
IMPLIFIED
ECEIVE
ECTION
AND
D
T
EFERENCE
ECLARATION CIRCUIT
D
M
IMING AND
H
H
ATA
P
P
........................................................................................................................................8
IAGRAM OF
S
H
P
ARALLEL
ARALLEL
ULTIPLIER
IGH
IGH
C
TTL R
P
P
P
ERIAL
IGH
D
L
ARALLEL
B
IN
LOCK AND
P
P
....................................................................................................................................4
....................................................................................................................................9
OOP
ARALLEL
R
ARALLEL
ARALLEL
ATA
B
LOCK
-
-S
ARALLEL
ARALLEL
..................................................................................................................................6
SPEED
ECOVERY UNIT REFERENCE CLOCK SETTINGS
O
-S
LOCK
............................................................................................................
PEED
UT OF THE
PEED
ECEIVE
I
R
F
F
NPUT
C
ILTERS
D
D
ECOVERY
D
REQUENCY
O
U
D
LOCK
XRT91L32 ...................................................................................................................................... 1
ATA
ATA
IAGRAM OF
S
O
S
D
D
NIT
UTPUT
IAGRAM OF
D
I
I
S
ERIAL
ERIAL
UTPUT
ATA
ATA
NPUT
NPUT
I
NTERFACE
ERIAL
ATA
O
O
O
P
.............................................................................................................................................. 16
R
UTPUTS
UTPUT
UTPUT
ERFORMANCE
XRT91L32 (T
I
I
........................................................................................................................................... 16
ECOVERY CONFIGURATIONS
NPUT
NPUT
R
D
U
I
I
T
D
NTERFACE
NTERFACE
T
ECOVERY
O
D
ATA
NIT
IMING
TABLE OF CONTENTS
ATA
IMING
ATA
SIPO ........................................................................................................................... 17
PTIONS
PISO ......................................................................................................................... 23
T
T
T
T
P
T
I
B
IMING
IMING
I
IMING
IMING
NPUT
ERFORMANCE
NPUT
IMING
I
.............................................................................................................................. 22
LOCK
NPUT
............................................................................................................................ 19
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
(D
B
B
B
....................................................................................................................... 11
....................................................................................................................... 23
(STS-12/STM-4 O
(STS-3/STM-1 O
OP
T
(STS-12/STM-4 O
(STS-3/STM-1 O
T
YPASS
LOCK
..................................................................................................................... 12
S
LOCK
IFFERENTIAL OR
T
IMING
IMING
PECIFICATION
IMING
V
IEW
............................................................................................................. 18
............................................................................................................. 21
............................................................................................................ 15
(STS-12/STM-4 O
(STS-3/STM-1 O
.......................................................................................................... 15
).......................................................................................................... 3
D
IAGRAM
I
................................................................................................. 24
.............................................................................................. 20
S
............................................................................................ 14
PERATION
PERATION
.......................................................................................... 13
INGLE
PERATION
PERATION
-E
PERATION
PERATION
NDED
) ........................................................................... 19
)........................................................................... 22
) ......................................................................... 19
)......................................................................... 22
) ................................................................... 11
) ............................................................... 13
) ............................................................. 13
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