XRT91L32ES Exar, XRT91L32ES Datasheet - Page 25

• Manufacturer Part Number: XRT91L32ES
• Description: LIN Transceivers SONET SDH 8 bit TRANCEIVER
• Manufacturer: Exar

Specifications of XRT91L32ES

• Product Category: LIN Transceivers
• Rohs: yes

xr
REV. 1.0.3
The PISO is used to convert 77.76 Mbps or 19.44 Mbps parallel data input to 622.08 Mbps STS-12/STM-1 or
155.52 Mbps STS-3/STM-1 serial data output respectively, which can interface to an optical module. The
PISO bit interleaves parallel data input into a serial bit stream taking the first bit from TXDI7, then the first bit
from TXDI6, and so on as shown in Figure 13.
F
The clock synthesizer uses a 77.76 MHz or a 19.44 MHz reference clock to generate the 622.08 MHz (for STS-
12/STM-4) or 155.52 MHz (for STS-3/STM-1) SONET/SDH transmit serial data rate frequency. Differential
LVPECL input REFCLKP/N accepts a clock reference of 77.76 MHz or 19.44 MHz to synthesize a high speed
622.08 MHz clock for STS-12/STM-4 or 155.52 MHz clock for STS-3/STM-1 applications. Optionally, if a
Differential LVPECL clock source is not available, TTLREFCLK can accept an LVTTL clock signal. The clock
synthesizer uses a PLL to lock-on to the differential input REFCLKP/N or Single-Ended input TTLREFCLK
reference clock. The REFCLKP/N input should be generated from an LVPECL crystal oscillator which has a
frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the necessary
accuracy required for SONET systems. If the TTLREFCLK
reference input should be tied to a LVTTL crystal oscillator with 20ppm accuracy. The two reference clocks are
XNOR’ed and the choice between the LVPECL and LVTTL clocks are controlled tying either REFCLKP or
TTLREFCLK to ground. Table 1, on page 11 shows the CMU reference clock frequency settings. Table 12
specifies the Clock Multiplier Unit’s requirements for the reference clock.
REF
REF
REF
REF
ECLK
ECLK
ECLK
3.3
3.4
IGURE
N
DUTY
JIT
JIT
TOL
JIT
JIT
JIT
AME
TXPCLK_IO
TXDI0
TXDI n
TXDI n+
13. S
TXDI7
Transmit Parallel Input to Serial Output (PISO)
Clock Multiplier Unit (CMU) and Re-Timer
b
b
b
b
IMPLIFIED
Reference clock duty cycle
Reference clock jitter (rms) with 19.44 MHz reference
Reference clock jitter (rms) with 77.76 MHz reference
Reference clock frequency tolerance
STS-3/STM-1 Electrical Clock output jitter (rms) with 19.44 MHz reference
STS-12/STM-4 Electrical Clock output jitter (rms) with 19.44 MHz reference
STS-3/STM-1 Electrical Clock output jitter (rms) with 77.76 MHz reference
n+
0
n
7
8-bit Parallel LVTTL Input Data
7
7
7
7
b
b
b
b
n+
0
n
7
6
6
6
6
T
b
b
b
b
n+
0
n
7
ABLE
5
5
5
5
b
b
b
b
n+
0
n
7
4
4
4
4
B
b
b
b
b
LOCK
n+
0
n
7
12: C
3
3
3
3
b
b
b
b
n+
0
n
7
2
2
2
2
b
b
b
b
n+
0
n
7
D
LOCK
1
1
1
1
IAGRAM OF
b
b
b
b
n+
0
n
7
0
0
0
0
77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)
M
ULTIPLIER
P
ARAMETER
2
PISO
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
U
NIT REQUIREMETNS FOR REFERENCE CLOCK
time (0)
b
7
7
23
b
6
7
1
1
b
5
7
b
4
155.52 Mbps STS-3/STM-1 serial data rate
7
b
3
7
622.08 Mbps STS-12/STM-4 or
b
2
reference clock is used, the TTLREFCLK
7 b
1
7 b
0
7
b
7
0
b
6
M
-20
0
40
IN
b
5
0
b
4
0
b
3
T
0
YP
1
5
2
b
2
0
b
1
0 b
0
M
0
+20
60
13
5
AX
XRT91L32
TXOP/N
mUI
mUI
mUI
U
ppm
NITS
%
ps
ps
rms
rms
rms