C8051F707-GQR Silicon Labs, C8051F707-GQR Datasheet - Page 163
C8051F707-GQR
Manufacturer Part Number
C8051F707-GQR
Description
8-bit Microcontrollers - MCU 16kB Cap Sense
Manufacturer
Silicon Labs
Datasheet
1.C8051F709-GQR.pdf
(306 pages)
Specifications of C8051F707-GQR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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Part Number:
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25. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled dur-
ing and after the reset. For V
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source. Pro-
gram execution begins at location 0x0000.
Px.x
Px.x
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
System
Clock
Comparator 0
+
-
Detector
Missing
C0RSEF
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
DD
CIP-51
Core
Handler
Monitor and power-on resets, the RST pin is driven low until the device
WDT
Figure 25.1. Reset Sources
PCA
EN
VDD
System Reset
Supply
Monitor
+
-
Rev. 1.0
Enable
(Software Reset)
SWRSF
'0'
Power On
Reset
Operation
C8051F70x/71x
FLASH
Errant
(wired-OR)
Reset
Funnel
RST
163
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