C8051T326-GMR Silicon Labs, C8051T326-GMR Datasheet - Page 257
C8051T326-GMR
Manufacturer Part Number
C8051T326-GMR
Description
8-bit Microcontrollers - MCU USB-OTP-16K-QFN28
Manufacturer
Silicon Labs
Datasheet
1.C8051T322-GQR.pdf
(292 pages)
Specifications of C8051T326-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
- Current page: 257 of 292
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28.3.2. 8-bit Timers with Auto-Reload
When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 28.8. TMR3RLL holds the reload value for TMR3L; TMR3RLH
holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, the external oscillator clock
source divided by 8, or the internal Low-frequency Oscillator. The Timer 3 Clock Select bits (T3MH and
T3ML in CKCON) select either SYSCLK or the clock defined by the Timer 3 External Clock Select bits
(T3XCLK[1:0] in TMR3CN), as follows:
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H over-
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
External Clock / 8
Internal LFO / 8
T3MH
SYSCLK / 12
0
0
0
0
1
T3XCLK[1:0] TMR3H Clock
T3XCLK[1:0]
00
01
10
11
00
01
11
X
SYSCLK
Figure 28.8. Timer 3 8-Bit Mode Block Diagram
Source
SYSCLK / 12
External Clock / 8
Reserved
Internal LFO
SYSCLK
0
1
1
0
C8051T620/621/320/321/322/323
M
H
T
3
M
T
3
L
CKCON
T
M
H
2
M
T
2
L
TR3
M
T
1
M
T
0
S
C
A
1
S
C
A
0
Rev. 1.1
TCLK
TCLK
TMR3RLH
TMR3RLL
TMR3H
TMR3L
T3ML
0
0
0
0
1
Reload
Reload
T3XCLK[1:0] TMR3L Clock
00
01
10
11
X
T3XCLK1
T3XCLK0
To ADC
TF3CEN
T3SPLIT
TF3LEN
TF3H
TF3L
TR3
Source
SYSCLK / 12
External Clock / 8
Reserved
Internal LFO
SYSCLK
Interrupt
257
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