C8051F585-IQR Silicon Labs, C8051F585-IQR Datasheet - Page 15
![no-image](/images/no-image-200.jpg)
C8051F585-IQR
Manufacturer Part Number
C8051F585-IQR
Description
8-bit Microcontrollers - MCU 50 MIPS 96 kB 8 kB SPI 2xUART
Manufacturer
Silicon Labs
Datasheet
1.C8051F585-IQR.pdf
(356 pages)
Specifications of C8051F585-IQR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F585-IQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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C8051F58x/F59x
SFR Definition 15.4. CCH0CN: Cache Control ........................................................... 146
SFR Definition 15.5. ONESHOT: Flash Oneshot Period ............................................ 146
SFR Definition 16.1. PCON: Power Control ................................................................ 149
SFR Definition 17.1. VDM0CN: VDD Monitor Control ................................................ 153
SFR Definition 17.2. RSTSRC: Reset Source ............................................................ 155
SFR Definition 18.1. EMI0CN: External Memory Interface Control ............................ 160
SFR Definition 18.2. EMI0CF: External Memory Configuration .................................. 161
SFR Definition 18.3. EMI0TC: External Memory Timing Control ................................ 166
SFR Definition 19.1. CLKSEL: Clock Select ............................................................... 175
SFR Definition 19.2. OSCICN: Internal Oscillator Control .......................................... 177
SFR Definition 19.3. OSCICRS: Internal Oscillator Coarse Calibration ...................... 178
SFR Definition 19.4. OSCIFIN: Internal Oscillator Fine Calibration ............................ 178
SFR Definition 19.5. CLKMUL: Clock Multiplier .......................................................... 180
SFR Definition 19.6. OSCXCN: External Oscillator Control ........................................ 182
SFR Definition 20.1. XBR0: Port I/O Crossbar Register 0 .......................................... 194
SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1 .......................................... 195
SFR Definition 20.3. XBR2: Port I/O Crossbar Register 2 .......................................... 196
SFR Definition 20.4. XBR3: Port I/O Crossbar Register 3 .......................................... 197
SFR Definition 20.5. P0MASK: Port 0 Mask Register ................................................. 198
SFR Definition 20.6. P0MAT: Port 0 Match Register .................................................. 198
SFR Definition 20.7. P1MASK: Port 1 Mask Register ................................................. 199
SFR Definition 20.8. P1MAT: Port 1 Match Register .................................................. 199
SFR Definition 20.9. P2MASK: Port 2 Mask Register ................................................. 200
SFR Definition 20.10. P2MAT: Port 2 Match Register ................................................ 200
SFR Definition 20.11. P3MASK: Port 3 Mask Register ............................................... 201
SFR Definition 20.12. P3MAT: Port 3 Match Register ................................................ 201
SFR Definition 20.13. P0: Port 0 ................................................................................. 202
SFR Definition 20.14. P0MDIN: Port 0 Input Mode ..................................................... 203
SFR Definition 20.15. P0MDOUT: Port 0 Output Mode .............................................. 203
SFR Definition 20.16. P0SKIP: Port 0 Skip ................................................................. 204
SFR Definition 20.17. P1: Port 1 ................................................................................. 204
SFR Definition 20.18. P1MDIN: Port 1 Input Mode ..................................................... 205
SFR Definition 20.19. P1MDOUT: Port 1 Output Mode .............................................. 205
SFR Definition 20.20. P1SKIP: Port 1 Skip ................................................................. 206
SFR Definition 20.21. P2: Port 2 ................................................................................. 206
SFR Definition 20.22. P2MDIN: Port 2 Input Mode ..................................................... 207
SFR Definition 20.23. P2MDOUT: Port 2 Output Mode .............................................. 207
SFR Definition 20.24. P2SKIP: Port 2 Skip ................................................................. 208
SFR Definition 20.25. P3: Port 3 ................................................................................. 208
SFR Definition 20.26. P3MDIN: Port 3 Input Mode ..................................................... 209
SFR Definition 20.27. P3MDOUT: Port 3 Output Mode .............................................. 209
SFR Definition 20.28. P3SKIP: Port 3Skip .................................................................. 210
SFR Definition 20.29. P4: Port 4 ................................................................................. 210
SFR Definition 20.30. P4MDOUT: Port 4 Output Mode .............................................. 211
SFR Definition 21.1. LIN0ADR: LIN0 Indirect Address Register ................................. 219
Rev. 1.2
15
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