C8051F714-GMR Silicon Labs, C8051F714-GMR Datasheet - Page 265
![no-image](/images/no-image-200.jpg)
C8051F714-GMR
Manufacturer Part Number
C8051F714-GMR
Description
8-bit Microcontrollers - MCU 8kB ADC Cap Sense
Manufacturer
Silicon Labs
Datasheet
1.C8051F709-GQR.pdf
(306 pages)
Specifications of C8051F714-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
- Current page: 265 of 306
- Download datasheet (2Mb)
33.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun-
ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
33.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 in the TCON register is set and the counter in TL0 is reloaded
from TH0. If Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload
value in TH0 is not changed. TL0 must be initialized to the desired value before enabling the timer for the
first count to be correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 in the TMOD register is logic 0 or when the input
signal INT0 is active as defined by bit IN0PL in register IT01CF (see Section “21.3. INT0 and INT1 External
Interrupts” on page 146 for details on the external input signals INT0 and INT1).
INT0
T0
Crossbar
Pre-scaled Clock
SYSCLK
IN0PL
GATE0
Figure 33.1. T0 Mode 0 Block Diagram
XOR
T0M
TR0
0
1
0
1
Rev. 1.0
G
A
T
E
1
C
T
1
/
M
T
1
1
TMOD
M
T
1
0
TCLK
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
(5 bits)
TL0
N
1
P
L
I
N
1
S
L
2
I
IT01CF
N
1
S
L
1
I
N
1
S
L
0
I
N
0
P
L
I
(8 bits)
C8051F70x/71x
TH0
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
I
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
265
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