PCA9555APW,118 NXP Semiconductors, PCA9555APW,118 Datasheet - Page 9

• Manufacturer Part Number: PCA9555APW,118
• Description: Interface - I/O Expanders 16b I2C BUS INTERUPT
• Manufacturer: NXP Semiconductors

Specifications of PCA9555APW,118

• Rohs: yes
• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Operating Current: 160 mA
• Output Current: 25 mA
• Power Dissipation: 200 mW
• Product Type: I/O Expanders
• Factory Pack Quantity: 2500

NXP Semiconductors
7. Bus transactions
PCA9555A
Product data sheet
6.4 Power-on reset
6.5 Interrupt output
7.1 Writing to the port registers
When power (from 0 V) is applied to V
in a reset condition until V
released and the PCA9555A registers and I
their default states. After that, V
operating voltage for a power-reset cycle. See
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode.
After time t
changes back to the original value or when data is read form the port that generated the
interrupt (see
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL
signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very
short) due to the resetting of the interrupt during this pulse. Any change of the I/Os after
resetting is detected and is transmitted as INT.
A pin configured as an output cannot cause an interrupt. Changing an I/O from an output
to an input may cause a false interrupt to occur, if the state of the pin does not match the
contents of the Input Port register.
The PCA9555A is an I
PCA9555A through write and read commands using I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
Data is transmitted to the PCA9555A by sending the device address and setting the least
significant bit to a logic 0 (see
is sent after the address and determines which register will receive the data following the
command byte.
Eight registers within the PCA9555A are configured to operate as four register pairs. The
four pairs are input port, output port, polarity inversion, configuration registers. After
sending data to one register, the next data byte is sent to the other register in the pair (see
Figure 7
the next byte is stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this
way, the host can continuously update a register pair independently of the other registers,
or the host can simply update a single register.
and
v(INT)
Figure
Figure 10
, the signal INT is valid. The interrupt is reset when data on the port
All information provided in this document is subject to legal disclaimers.
Low-voltage 16-bit I
8). For example, if the first byte is sent to Output Port 1 (register 3),
Rev. 1 — 11 September 2012
2
C-bus slave device. Data is exchanged between the master and
and
DD
Figure
has reached V
Figure 4 “PCA9555A device
DD
must be lowered to below V
11). Resetting occurs in the Read mode at the
DD
2
, an internal power-on reset holds the PCA9555A
C-bus I/O port with interrupt and weak pull-up
POR
2
C-bus/SMBus state machine initializes to
Section 8.2 “Power-on reset
. At that time, the reset condition is
2
C-bus. The two communication
address”). The command byte
PORF
PCA9555A
and back up to the
© NXP B.V. 2012. All rights reserved.
requirements”.
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