IS25LD020-JDLE ISSI, IS25LD020-JDLE Datasheet - Page 9

• Manufacturer Part Number: IS25LD020-JDLE
• Description: Flash 2M 2.3-3.6V 100Mhz Serial Flash
• Manufacturer: ISSI

Specifications of IS25LD020-JDLE

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 2 Mbit
• Architecture: Uniform
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.3 V
• Maximum Operating Current: 15 mA
• Operating Temperature: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Organization: 256 K x 8

DEVICE OPERATION
The IS25CD512/010 and IS25LD020 utilize an 8-bit
instruction register. Refer to Table 10 Instruction Set for
details of the Instructions and Instruction Codes. All
instructions, addresses, and data are shifted in with the most
significant bit (MSB) first on Serial Data Input (SI). The input
data on SI is latched on the rising edge of Serial Clock (SCK)
after Chip Enable (CE#) is driven low (V
sequence starts with a one-byte instruction code and is
Table 10. Instruction Set
Instruction Name
RDID
JEDEC ID READ
RDMDID
WREN
WRDI
RDSR
WRSR
READ
FAST_READ
FRDO
PAGE_ PROG
SECTOR_ER
BLOCK_ER
CHIP_ER
HOLD OPERATION
HOLD# is used in conjunction with CE# to select the
IS25CD512/010 and IS25LD020. When the devices are
selected and a serial sequence is underway, HOLD# can
be used to pause the serial communication with the
master device without resetting the serial sequence. To
Integrated Silicon Solution, Inc.- www.issi.com
Rev. D
2/12/2013
Hex Code
D7h/20h
C7h/60h
ABh
D8h
9Fh
0Bh
3Bh
90h
06h
04h
05h
01h
03h
02h
Operation
Read Manufacturer and Product ID
Read Manufacturer and Product ID by JEDEC ID
Command
Read Manufacturer and Device ID
Write Enable
Write Disable
Read Status Register
Write Status Register
Read Data Bytes from Memory at Normal Read Mode
Read Data Bytes from Memory at Fast Read Mode
Fast Read Dual Output
Page Program Data Bytes Into Memory
Sector Erase
Block Erase
Chip Erase
IL
). Every instruction
followed by address bytes, data bytes, or both address bytes
and data bytes, depending on the type of instruction. CE#
must be driven high (V
sequence has been shifted in.
The timing for each instruction is illustrated in the following
operational descriptions.
pause, HOLD# is brought low while the SCK signal is low.
To resume serial communication, HOLD# is brought high
while the SCK signal is low (SCK may still toggle during
HOLD). Inputs to SlO will be ignored while SO is in the
high impedance state.
IH
) after the last bit of the instruction
IS25CD512/010
4 Bytes
1 Byte
4 Bytes
1 Byte
1 Byte
1 Byte
2 Bytes
4 Bytes
5 Bytes
5 Bytes
4 Bytes +
256B
4 Bytes
4 Bytes
1 Byte
Command
Cycle
IS25LD020
Maximum
Frequency
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
33 MHz
100 MHz
100 MHz
50 MHz
100 MHz
100 MHz
100 MHz
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