IS25LQ016-JKLE ISSI, IS25LQ016-JKLE Datasheet - Page 8

• Manufacturer Part Number: IS25LQ016-JKLE
• Description: Flash 16M 2.3-3.6V 104Mhz Serial Flash
• Manufacturer: ISSI

Specifications of IS25LQ016-JKLE

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 16 Mbit
• Architecture: Uniform
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.3 V
• Maximum Operating Current: 12 mA
• Operating Temperature: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: WSON-8
• Organization: 2048 K x 8

REGISTERS (CONTINUED)
STATUS REGISTER
Refer to Tables 5 and 6 for Status Register Format and
Status Register Bit Definitions.
The BP0, BP1, BP2, BP3 and SRWD are non-volatile
memory cells that can be written by a Write Status
Register (WRSR) instruction. The default value of the
BP2, BP1, BP0, and SRWD bits were set to “0” at
factory. The Status Register can be read by the Read
Status Register (RDSR). Refer to Table 10 for
Instruction Set.
The function of Status Register bits are described as
follows:
WIP bit: The Write In Progress (WIP) bit is read-only,
and can be used to detect the progress or completion
of a program or erase operation. When the WIP bit is
“0”, the device is ready for a write status register,
program or erase operation. When the WIP bit is “1”,
the device is busy.
WEL bit: The Write Enable Latch (WEL) bit indicates
the status of the internal write enable latch. When the
WEL is “0”, the write enable latch is disabled, and all
write operations, including write status register, write
configuration register, page program, sector erase,
block and chip erase operations are inhibited. When
the WEL bit is “1”, write operations are allowed. The
WEL bit is set by a Write Enable (WREN) instruction.
Each write register, program and erase instruction
must be preceded by a WREN instruction. The WEL bit
can be reset by a Write Disable (WRDI) instruction. It
will automatically be the reset after the completion of a
write instruction.
Table 5. Status Register Format
* The default value of the BP3, BP2, BP1, BP0, and SRWD bits were set to “0” at factory.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 0A
2/1/2013
Default (flash bit)
SRWD
Bit 7
0
Bit 6
QE
0
Bit 5
BP3
0
Bit 4
BP2
0
BP3, BP2, BP1, BP0 bits: The Block Protection (BP3,
BP2, BP1 and BP0) bits are used to define the portion
of the memory area to be protected. Refer to Tables 7,
8 and 9 for the Block Write Protection bit settings.
When a defined combination of BP3, BP2, BP1 and
BP0 bits are set, the corresponding memory area is
protected. Any program or erase operation to that area
will be inhibited.Note: a Chip Erase (CHIP_ER)
instruction is executed only if all the Block Protection
Bits are set as “0”s.
SRWD bit: The Status Register Write Disable (SRWD)
bits operates in conjunction with the Write Protection
(WP#) signal to provide a Hardware Protection Mode.
When the SRWD is set to “0”, the Status Register is
not write-protected. When the SRWD is set to “1” and
the WP# is pulled low (V
(SRWD, BP3, BP2, BP1, BP0) become read-only, and
a WRSR instruction will be ignored. If the SRWD is set
to “1” and WP# is pulled high (V
can be changed by a WRSR instruction.
QE bit: The Quad Enable (QE) is a non-volatile bit in
the status register that allows Quad operation. When
the QE bit is set to “0”,the pin WP# and HOLD# are
enable. When the QE bit is set to “1”, the pin IO2 and
IO3 are enable.
WARNING: The QE bit should never be set to a 1
during standard SPI or Dual SPI operation if the
WP# or HOLD# pins are tied directly to the power
supply or ground.
Bit 3
BP1
0
Bit 2
BP0
0
IL
), the bits of Status Register
Bit 1
WEL
0
IS25LQ016
IH
), the Status Register
Bit 0
WIP
0
8