IS25LQ016 ISSI [Integrated Silicon Solution, Inc], IS25LQ016 Datasheet
IS25LQ016
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IS25LQ016 Summary of contents
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... Chip Erase 5s (Typ) GENERAL DESCRIPTION The IS25LQ016 are 16 Mbit Serial Peripheral Interface (SPI) Flash memories, providing single-, dual or quad- output. The devices are designed to support a 50 MHz fclock rate in normal read mode, and 104 MHz in fast read (Quad output is 100MHz), the fastest in the industry. The devices use a single low voltage power supply, ranging from 2 ...
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... PDIP Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface Vcc CE (IO1) HOLD# (IO3) 3 WP# (IO2) SCK 4 GND ) SI (IO0 Vcc 8 HOLD#(IO3) NC(IO3) SCK SI(IO0) IS25LQ016 8 Vcc 7 HOLD#(IO3) 6 SCK ) 5 SI (IO0 8-Contact WSON 2 ...
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... When the QE bit of Status Register-2 is set for ‘‘1’’, the function is Serial Data Input & Output (for 4xI/O read mode) Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface IS25LQ016 3 ...
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... Mbit Single Operating Voltage Serial Flash Memory With 104 BLOCK DIAGRAM WP# (IO2) SI (IO0) SO (IO1) HOLD# (IO3) Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface IS25LQ016 4 ...
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... Mbit Single Operating Voltage Serial Flash Memory With 104 SPI MODES DESCRIPTION Multiple IS25LQ016 devices can be connected on the SPI serial bus and controlled by a SPI Master, i.e. microcontroller, as shown in Figure 1. The devices support either of two SPI modes: Mode 0 (0, 0) Mode 3 (1, 1) Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices) ...
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... Configuration Register: 1. Configurable sector size: The memory array of IS25LQ016 is divided into uniform 4 KByte sectors or uniform 64 KByte blocks (a block consists of sixteen adjacent sectors). Table 1 illustrates the memory map of the devices. ...
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... Mbit Single Operating Voltage Serial Flash Memory With 104 BLOCK/SECTOR ADDRESSES Table 1. Block/Sector Addresses of IS25LQ016 Block No. Memory Density (64Kbyte) Block 0 Block 1 : Block 7 Block 8 16Mbit : : Block 15 Block Block 31 Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface Sector Sector No ...
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... SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or ground. Bit 6 Bit 5 Bit 4 Bit 3 QE BP3 BP2 BP1 IS25LQ016 ), the bits of Status Register IL ), the Status Register IH Bit 2 Bit 1 Bit 0 BP0 WEL WIP ...
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... Quad output function enable Status Register Write Disable: (See Table 10 for details) Bit 7 SRWD "0" indicates the Status Register is not write-protected (default) "1" indicates the Status Register is write-protected Table 9. Block Write Protect Bits for IS25LQ016C Status Register Bits BP3 BP2 BP1 0 ...
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... Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface The IS25LQ016 also provides two software write protection features: a. Before the execution of any program, erase or write status register instruction, the Write Enable Latch (WEL) bit must be enabled by executing a Write Enable (WREN) instruction ...
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... Read 65 bytes of Security area Raw HOLD OPERATION HOLD# is used in conjunction with CE# to select the IS25LQ016. When the devices are selected and a serial sequence is underway, HOLD# can be used to pause the serial communication with the master device without resetting the serial sequence. Integrated Silicon Solution, Inc.- www.issi.com Rev ...
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... BUSY equals 1) the instruction is ignored and will not have any effects on the current cycle Table 12. Product Identification Product Identification Manufacturer ID Device ID: IS25LQ016C Dummy Bytes Device ID1 IS25LQ016 time duration. If the RES1 Data First Byte Second Byte Device ID1 Device ID2 14h Device ID1 ...
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... MHz Dual- or 100MHz Quad-Output SPI Bus Interface by the first Device ID1 (14h) and the Device ID 2(45h), in the case of the IS25LQ016C), each bit shifted out during the falling edge of SCK. If CE# stays low after the last bit of the Device ID is shifted out, the Manufacturer ID and Device ID will loop until CE# is pulled high ...
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... then device followed by the first manufacture ID (9Dh) and then second manufacture ID (7Fh). The manufacture and device ID can be read continuously, alternating from one to the others. The instruction is completed by driving CE# high. IS25LQ016 ID1 and the second ID1 will be read first, then 14 ...
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... ADDRESS will output the 1st manufacture ID (9Dh) first -> device ID1 -> 2nd manufacture ID (7Fh) ADDRESS will output the device ID1 -> 1st manufacture ID (9D) -> 2nd manufacture ID (7Fh) Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface IS25LQ016 15 ...
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... WRITE ENABLE OPERATION The Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL bit of the IS25LQ016 is reset to the write –protected state after power-up. The WEL bit must be write enabled before any write operation, including sector, block erase, chip Figure 6 ...
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... Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface instruction, which can be used to check the progress or completion of an operation by reading the WIP bit of Status Register. or “1”s into the non-volatile BP3, BP2, BP1, BP0 and SRWD bits. IS25LQ016 17 ...
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... Mbit Single Operating Voltage Serial Flash Memory With 104 DEVICE OPERATION (CONTINUED) READ COMMAND (READ DATA) OPERATION The Read Data (READ) instruction is used to read memory data of a IS25LQ016under normal mode running up to 50MHz. The READ instruction code is transmitted via the Sl line, followed by three address bytes (A23 - A0) of the first memory location to be read ...
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... FAST_READ instruction. The FAST_READ instruction is terminated by driving CE# high ( Fast Read Data instruction is issued while IH , during the an Erase, Program or Write cycle is in process (BUSY=1) CT the instruction is ignored and will not have any effects on the current cycle IS25LQ016 19 ...
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... BYTE ADDRESS DATA OUT IS25LQ016 ). If a FRDO ... ... DATA OUT 2 1 ...
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... Mode Reset (FFh) command. In subsequent FRDIO execution, the command code is not input, saving timing cycles as described in Figure 16. , during the instruction is issued while an Erase, Program or Write CT cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle IS25LQ016 ). FRDIO 21 ...
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... FRQO instruction. FRQO instruction is terminated by driving CE# high (V instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle IS25LQ016 ...
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... Mbit Single Operating Voltage Serial Flash Memory With 104 DEVICE OPERATION (CONTINUED) Figure 17. Fast Read Quad-Output Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface IS25LQ016 23 ...
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... Mode Reset (FFh) command. In subsequent FRDIO execution, the command code is not input, saving cycles as described in Figure 19. is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle IS25LQ016 ). FRQIO instruction 24 ...
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... DATA OUT 2 DATA OUT 3 DATA OUT IS25LQ016 BYTE ADDRESS MODE BITS ...
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... MODE BITS 4 Dummy Clock command after a system reset. The timing sequence is different depending whether the MR command is used after an FRDIO or FRQIO, as shown in Figure 20. IS25LQ016 DATA OUT 1 DATA OUT 2 26 ...
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... Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s. A byte cannot be reprogrammed without first erasing the whole sector or block. IS25LQ016 27 ...
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... Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s. A byte cannot be reprogrammed without first erasing the whole sector or block. IS25LQ016 28 ...
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... Mbit Single Operating Voltage Serial Flash Memory With 104 Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface 00110010b IS25LQ016 29 ...
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... Refer to Figure 23 for Block Erase Sequence. CHIP_ER COMMAND (CHIP ERASE) OPERATION A Chip Erase (CHIP_ER) instruction erases the entire memory array of a IS25LQ016. Before the execution of CHIP_ER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after completion of a chip erase operation ...
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... Mbit Single Operating Voltage Serial Flash Memory With 104 DEVICE OPERATION (CONTINUED) Figure 22. Sector Erase Sequence Figure 23. Block Erase Sequence Figure 24. Chip Erase Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface IS25LQ016 31 ...
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... Note: 1 n 256 Figure 30. Program information Raw Sequence Note: 1. The SIR address is from 000000h to 0000FFh. 2. The SIR protection bit is in the address 000100h. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface IS25LQ016 ) is initiated. While the potp 32 ...
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... Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface 256 bytes of the OTP memory array can be programmed. 256 bytes of the OTP memory array are read-only and 256 (control byte) is set to ‘0’, the IS25LQ016 256 bytes of the OTP 33 ...
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... This means that the read OTP (ROTP) instruction must be sent with a maximum of 256 bytes to read, since once the 256 Fig 33. Read Security information Row instruction Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface th byte has been read, the same (256 IS25LQ016 th ) byte keeps being read on the SO pin. 34 ...
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... 130 2 2.3V < V < 3. -100 IS25LQ016 o C IS25LQ016 105 - - - 105 - 125 C 2.3 V – 3 ...
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... Chip Erase Time (16Mb) t Page Program Time PP t res1 Write Status Register time w Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface = 2 3 Min IS25LQ016 Typ Max Units 0 104 MHz 0 50 MHz ...
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... Mbit Single Operating Voltage Serial Flash Memory With 104 AC CHARACTERISTICS (CONTINUED) SERIAL INPUT/OUTPUT TIMING Note: 1. For SPI Mode 0 (0,0) Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface (1) IS25LQ016 37 ...
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... Note: These parameters are characterized but not 100% tested. OUTPUT TEST LOAD 30pf Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface Max Units INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL IS25LQ016 Conditions OUT 38 ...
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... At Power-down, when Vcc drops from the operating voltage, to below the Vwi, all write operations are disabled and the device does not respond to any write instruction. All Write Commands are Rejected tVCE tPUW Parameter IS25LQ016 Read Access Allowed Device fully accessible Time Min. Max. Unit 10 us ...
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... From writing erase command to erase completion 0.5 0.7 From writing program command to program completion 10 Min Typ Unit 100,000 Cycles 20 Years 2,000 Volts 200 Volts 100 + I mA CC1 IS25LQ016 Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78 40 ...
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... Mbit Single Operating Voltage Serial Flash Memory With 104 PACKAGE TYPE INFORMATION (CONTINUED 8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit (SOIC) Package (measure in millimeters) Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface IS25LQ016 41 ...
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... Mbit Single Operating Voltage Serial Flash Memory With 104 PACKAGE TYPE INFORMATION (CONTINUED) JP 8-Contact Ulta-Thin Small Outline No-Lead (WSON) Package (measure in millimeters) Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface IS25LQ016 42 ...
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... Mbit Single Operating Voltage Serial Flash Memory With 104 PACKAGE TYPE INFORMATION (CONTINUED) JA 8-pin 300mil wide body, Plastic Dual In-Line Package PDIP (measure in millimeters) Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface IS25LQ016 43 ...
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... Mbit Single Operating Voltage Serial Flash Memory With 104 PACKAGE TYPE INFORMATION (CONTINUED 8-Pin 208mil VSOP Package Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface IS25LQ016 44 ...
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... Safe Guard function is a security function for customer to protect by sector (4Kbyte). Every sector has one bit register to decide it will under safe guard protect or not. (“0”means protect and “1” means not protect by safe guard.) IS25LQ016 (sector 0~sector 511) Mapping table for safe guard register ...
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... Fig c. shows the complete steps for program safe guard register. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface ) after the data comes out A23-A0 IS25LQ016 byte st 1 byte D7-D0 D7-D0 ...
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... Mbit Single Operating Voltage Serial Flash Memory With 104 Fig b. Erase safe guard register Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface IS25LQ016 47 ...
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... Mbit Single Operating Voltage Serial Flash Memory With 104 Fig c. program safe guard register Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface st 1 byte 2nd byte IS25LQ016 48 ...
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... Sector Lock command. The instruction code is followed by a 24-bit address specifying the target sector, but A0 through A11 are not decoded. The remaining sectors within the same block remain in read-only mode. IS25LQ016 Command Maximum Cycle Frequency 4 Bytes 100 MHz ...
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... Figure e. Sector Lock Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface one sector can be enabled at a time. The remaining sectors within the same block remain in read-only mode. IS25LQ016 50 ...
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... I = Industrial Grade (-40°C to +85° Automotive, A1 Grade (-40°C to +85° Automotive, A2 Grade (-40°C to +105° Automotive, A3 Grade (-40°C to +125°C) Environmental Attribute L = Lead-free (Pb-free) package Package Type JB = 8-pin SOIC 150mil JP = 8-pin WSON JA = 8-pin PDIP JF = 8-pin VVSOP 150mil Device Number IS25LQ016 IS25LQ016 51 ...
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... IS25LQ016-JALE IS25LQ016-JFLE IS25LQ016-JBLI IS25LQ016-JPLI IS25LQ016-JALI IS25LQ016-JFLI 16M 104 IS25LQ016-JBLA1 IS25LQ016-JPLA1 IS25LQ016-JALA1 IS25LQ016-JFLA1 IS25LQ016-JBLA2 IS25LQ016-JPLA2 IS25LQ016-JALA2 IS25LQ016-JFLA2 Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2012 MHz Dual- or 100MHz Quad-Output SPI Bus Interface Package 8-pin SOIC 208-mil 8-pin WSON 8-pin PDIP 8-pin VSOP 208mil ...