IS25LD020-JKLE ISSI, IS25LD020-JKLE Datasheet - Page 6

• Manufacturer Part Number: IS25LD020-JKLE
• Description: Flash 2M 2.3-3.6V 100Mhz Serial Flash
• Manufacturer: ISSI

Specifications of IS25LD020-JKLE

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 2 Mbit
• Architecture: Uniform
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.3 V
• Maximum Operating Current: 15 mA
• Operating Temperature: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: WSON-8
• Organization: 256 K x 8

REGISTERS (CONTINUED)
STATUS REGISTER
Refer to Tables 5 and 6 for Status Register Format and
Status Register Bit Definitions.
The BP0, BP1, BP2, and SRWD are volatile memory cells
that can be written by a Write Status Register (WRSR)
instruction. The default value of the BP2, BP1, BP0 were set
to “0” and SRWD bits was set to “0” at factory. Once a “0” or
“1”is written, it will not be changed by device power-up or
power-down, and can only be altered by the next WRSR
instruction. The Status Register can be read by the Read
Status Register (RDSR). Refer to Table 10 for Instruction
Set.
The function of Status Register bits are described as follows:
WIP bit: The Write In Progress (WIP) bit is read-only, and
can be used to detect the progress or completion of a
program or erase operation. When the WIP bit is “0”, the
device is ready for a write status register, program or erase
operation. When the WIP bit is “1”, the device is busy.
WEL bit: The Write Enable Latch (WEL) bit indicates the
status of the internal write enable latch. When the WEL is “0”,
the write enable latch is disabled, and all write operations,
including write status register, page program, sector erase,
block and chip erase operations are inhibited. When the WEL
bit is “1”, write operations are allowed. The WEL bit is set by
Table 5. Status Register Format
Integrated Silicon Solution, Inc.- www.issi.com
Rev. D
2/12/2013
Default (flash bit)
SRWD1
Bit 7
0
Bit 6
Reserved
0
Bit 5
Bit 4
BP2
0
a Write Enable (WREN) instruction. Each write register,
program and erase instruction must be preceded by a WREN
instruction. The WEL bit can be reset by a Write Disable
(WRDI) instruction. It will automatically be the reset after the
completion of a write instruction.
BP2, BP1, BP0 bits: The Block Protection (BP2, BP1, BP0)
bits are used to define the portion of the memory area to be
protected. Refer to Tables 7, 8 and 9 for the Block Write
Protection bit settings. When a defined combination of BP2,
BP1 and BP0 bits are set, the corresponding memory area is
protected. Any program or erase operation to that area will
be inhibited. Note: a Chip Erase (CHIP_ER) instruction is
executed successfully only if all the Block Protection Bits are
set as “0”s.
SRWD bit: The Status Register Write Disable (SRWD) bit
operates in conjunction with the Write Protection (WP#)
signal to provide a Hardware Protection Mode. When the
SRWD is set to “0”, the Status Register is not write-protected.
When the SRWD is set to “1” and the WP# is pulled low
(VIL), the volatile bits of Status Register (SRWD, BP2, BP1,
BP0) become read-only, and a WRSR instruction will be
ignored. If the SRWD is set to “1” and WP# is pulled high
(VIH), the Status Register can be changed by a WRSR
instruction.
Bit 3
BP1
0
Bit 2
BP0
0
Bit 1
WEL
0
IS25CD512/010
IS25LD020
Bit 0
WIP
0
6