S25FL204K0TMFI040 Spansion, S25FL204K0TMFI040 Datasheet - Page 13

• Manufacturer Part Number: S25FL204K0TMFI040
• Description: Flash 4Mb 3V 85MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL204K0TMFI040

• Rohs: yes
• Memory Type: NOR Flash
• Memory Size: 4 MB
• Interface Type: SPI
• Access Time: 5 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-8

7. Write Protection
January 17, 2013 S25FL204K_00_06
Some basic protection against unintended changes to stored data is provided and controlled purely by the
hardware design. These protection mechanisms in the S25FL204K device are described below:
 Power-On Reset and an internal timer (t
 Program, Erase and Write Status Register instructions are checked that they consist of a number of clock
 All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write
 The Block Protect (BP3, BP2, BP1, and BP0) bits allow part of the memory to be configured as read-only.
 The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status Register
 In addition to the low power consumption feature, the Deep Power-down mode offers extra software
to a 1, the Write Status Register instruction is locked out while the WP# pin is low. When the WP# pin is
high the Write Status Register instruction is allowed.
power supply is outside the operating specification.
pulses that is a multiple of eight, before they are accepted for execution.
Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:
This is the Software Protected Mode (SPM).
Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored except
one particular instruction (the Release from Deep Power-down instruction).
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction completion or
BP3
Page Program (PP) instruction completion or Sector Erase (SE) instruction completion or Block Erase
(BE) instruction completion or Chip Erase (CE) instruction completion
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D a t a
BP2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Table 7.1 Protected Area Sizes Block Organization — S25FL204K
S h e e t
Status Bit
BP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
( P r e l i m i n a r y )
S25FL204K
PUW
BP0
) can provide protection against inadvertent changes while the
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
10 (124 sectors, sector 0th~123rd)
11 (120 sectors, sector 0th~119th)
12 (112 sectors, sector 0th~111th)
9 (126 sectors, sector 0th~125th)
13 (96 sectors, sectors 0th~95th)
14 (64 sectors, sectors 0th~63rd)
2 (2 blocks, block 6th~7th)
3 (4 blocks, block 4th~7th)
1 (1 block, block 7th)
15 (128 sectors, all)
Protect Blocks
4 (8 blocks, all)
5 (8 blocks, all)
6 (8 blocks, all)
7 (8 blocks, all)
0 (None)
8 none
13