78Q2123R/F1 Maxim Integrated, 78Q2123R/F1 Datasheet - Page 11

• Manufacturer Part Number: 78Q2123R/F1
• Description: Ethernet ICs
• Manufacturer: Maxim Integrated

Specifications of 78Q2123R/F1

• Rohs: yes

DS_21x3_001
2 Pin Description
2.1
2.2
Rev. 1.6
Type
Signal
TX_CLK
TX_EN
TXD[3:0]
TX_ER
CRS
COL
RX_CLK
RX_DV
CIU
CIS
CO
A
S
Legend
MII (Media Independent Interface)
Description
Analog Pin
TTL-level Input with Pull-up
TTL-level Input with Schmitt Trigger
CMOS Output
Supply
Pin
[20:17]
15
16
14
22
21
12
11
Type
COZ
COZ
COZ
COZ
COZ
CI
CI
CI
Description
TRANSMIT CLOCK: TX_CLK is a continuous clock, which provides a
timing reference for the TX_EN, TX_ER and TXD[3:0] signals from the
MAC. The clock frequency is 25 MHz in 100BASE-TX mode and 2.5 MHz
in 10BASE-T mode. This pin is tri-stated in isolate mode and the TXHIM
mode.
TRANSMIT ENABLE: TX_EN is asserted by the MAC to indicate that
valid data for transmission is present on the TXD[3:0] pins.
TRANSMIT DATA: TXD[3:0] receives data from the MAC for transmission
on a nibble basis. This data is captured on the rising edge of TX_CLK
when TX_EN is high.
TRANSMIT ERROR: TX_ER is asserted high by the MAC to request that
an error code-group be transmitted when TX_EN is high. In PCS bypass
mode, this pin becomes the MSB of the transmit 5-bit code group.
CARRIER SENSE: When the 78Q2123/78Q2133 are not in repeater
mode, CRS is high whenever a non-idle condition exists on either the
transmitter or the receiver. In repeater mode, CRS is only active when a
non-idle condition exists on the receiver. This pin is tri-stated in isolate
mode.
COLLISION: COL is asserted high when a collision has been detected on
the media. In 10BASE-T mode COL is also used for the SQE test function.
This pin is tri-stated in isolate mode. During half duplex operation, the
rising edge of COL will occasionally occur upon the rising edge of
TX_CLK.
RECEIVE CLOCK: RX_CLK is a continuous clock, which provides a
timing reference to the MAC for the RX_DV, RX_ER and RXD[3:0] signals.
The clock frequency is 25 MHz in 100BASE-TX mode and 2.5 MHz in
10BASE-T mode. To reduce power consumption in 100BASE-TX mode,
the 78Q2123/78Q2133 provide an optional mode, enabled through
MR16.0, in which RX_CLK is held inactive (low) when no receive data is
detected. This pin is tri-stated in isolate mode.
RECEIVE DATA VALID: RX_DV is asserted high to indicate that valid
data is present on the RXD[3:0] pins. In 100BASE-TX mode, it transitions
high with the first nibble of the preamble and is pulled low when the last
data nibble has been received. In 10BASE-T mode it transitions high when
the start-of-frame delimiter (SFD) is detected. This pin is tri-stated in
isolate mode.
Type
COZ
CIO
CI
G
Description
TTL-level Input
TTL-compatible Bi-directional Pin
Tristate-able CMOS Output
Ground
78Q2123/78Q2133 Data Sheet
11