78Q2123-DB Maxim Integrated Products, 78Q2123-DB Datasheet
78Q2123-DB
Specifications of 78Q2123-DB
Related parts for 78Q2123-DB
78Q2123-DB Summary of contents
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... Ethernet market, tailored specifically to the needs of game consoles, broadband modems, printers, set top boxes and audio/visual equipment designed for low-power consumption and operates from a single 3.3V supply. The 78Q2123 is rated for commercial temperature range and the 78Q2133 is rated for industrial temperature range. 100M ...
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... Data Sheet 1 Functional Description .................................................................................................................. 5 1.1 General ................................................................................................................................... 5 1.1.1 Power Management .................................................................................................... 5 1.1.2 Analog Biasing and Supply Regulation ........................................................................ 5 1.1.3 Clock Selection............................................................................................................ 5 1.1.4 Transmit Clock Generation .......................................................................................... 5 1.1.5 Receive Signal Qualification ........................................................................................ 6 1.1.6 Receive Clock Recovery.............................................................................................. 6 1.2 100BASE-TX OPERATION ..................................................................................................... 6 1.2.1 100BASE-TX Transmit ................................................................................................ 6 1.2.2 100BASE-TX Receive ................................................................................................. 6 1.2.3 PCS Bypass Mode (Auto-negotiate must be off) .......................................................... 6 1 ...
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... Isolation Transformers........................................................................................................... 33 4.9 Reference Crystal ................................................................................................................. 33 4.9.1 External XTLP Oscillator Characteristics .................................................................... 34 5 Package Pin Designations .......................................................................................................... 35 6 32-Pin QFN Mechanical Specifications ....................................................................................... 36 6.1 Recommended Pcb Land Pattern Dimensions ....................................................................... 37 6.1.1 Recommended PCB Land Pattern Dimensions .......................................................... 37 7 Ordering Information ................................................................................................................... 37 Revision History .................................................................................................................................. 38 Rev. 1.6 78Q2123/78Q2133 Data Sheet 3 ...
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... Figure 1: RST Pulse Duration ................................................................................................................ 25 Figure 2: Transmit Inputs to the 78Q2123/78Q2133 ............................................................................... 25 Figure 3: Receive Outputs from the 78Q2123/78Q2133 ......................................................................... 26 Figure 4: MDIO as an Input to the 78Q2123/78Q2133 ............................................................................ 26 Figure 5: MDIO as an Output to the 78Q2123/78Q2133 ......................................................................... 27 Figure 6: MDIO Interface Output Timing ................................................................................................. 28 Figure 7: Application Diagram for 78Q2123/78Q2133 ............................................................................ 32 Figure 8: External XTLP Oscillator Characteristics ................................................................................. 34 Figure 9: Package Pin Designations ...
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... The on-chip regulator is not affected by the power-down mode. 1.1.3 Clock Selection The 78Q2123/78Q2133 have an on-chip crystal oscillator which can also be driven by an external oscillator. In this mode of operation MHz crystal should be connected between the XTLP and XTLN pins. ...
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... The 78Q2123/78Q2133 can compensate for cable loss 10dB at 16 MHz. This loss is represented as test_chan_5 in Annex A of the ANSI X3.263:199X. The equalized MLT-3 data signal is bi-directionally sliced and the resulting NRZI bit-stream is presented to the CDR where it is re-timed and decoded to NRZ format ...
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... OPERATION 1.3.1 10BASE-T Transmit The 78Q2123/78Q2133 take 4-bit parallel NRZ data via the MII interface and passes it through a parallel to serial converter. The data is then passed through a Manchester encoder, pre-emphasis pulse-shaper, media filter, and finally to the twisted-pair line driver. The pulse-shaper and filter ensure the output waveforms meet the voltage template and spectral content requirements detailed in Clause 14 of IEEE-802 ...
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... With auto-negotiation enabled, the 78Q2123/78Q2133 will start sending fast link pulses at power on, loss of link or upon a command to restart. At the same time, it will look for either 10BASE-T idle, 100BASE-TX idle, or fast link pulses from its link partner. If either idle pattern is detected, the 78Q2123/78Q2133 configure themselves in half-duplex mode at the appropriate speed detects fast link pulses, it decodes and analyzes the link code transmitted by the link partner ...
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... This allows for faster programming of the registers register does not exist at an address indicated by the REGAD field or if the PHYAD field does not match the 78Q2123/78Q2133 PHYAD, a read of the MDIO port will return all ones. For a write operation, the data is shifted in and loaded into the appropriate register after the sixteenth data bit has been received ...
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... The default status of these LEDs are “Link OK” for LED0 and “ Activity” for LED1. 1.6.2 Interrupt Pin The 78Q2123 and 78Q2133 have an Interrupt pin (INTR) that is asserted whenever any of the eight interrupt bits of MR17.7:0 are set. These interrupt bits can be disabled via the MR17.15:8 Interrupt Enable bits ...
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... MSB of the transmit 5-bit code group. CRS 22 COZ CARRIER SENSE: When the 78Q2123/78Q2133 are not in repeater mode, CRS is high whenever a non-idle condition exists on either the transmitter or the receiver. In repeater mode, CRS is only active when a non-idle condition exists on the receiver. This pin is tri-stated in isolate mode ...
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... MANAGEMENT DATA CLOCK: MDC is the clock used for transferring data via the MDIO pin. MDIO 1 CIO MANAGEMENT DATA INPUT/OUTPUT: MDIO is a bi-directional port used to access management registers within the 78Q2123/78Q2133. This pin requires an external pull-up resistor as specified in IEEE-802.3. 2.3 Control and Status Signal Pin ...
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... LEDBTX is OFF during auto-negotiation. BASE-T: ON for 10BASE-T connection and OFF for other connections. LEDBT is OFF during auto-negotiation. FULL DUPLEX: ON when in full duplex mode and OFF when in half duplex mode. LINK/ACT: ON for link, blink for activity. Rev. 1.6 78Q2123/78Q2133 Data Sheet 13 ...
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... MDIO pin will not be enabled as an output, as per the IEEE 802.3 specification. All of the registers except those that are unique to the 78Q2123/78Q2133 will respond to the broadcast PHYAD value of ‘00000’. The registers specific to the 78Q2123/78Q2133 occupy address space MR16-24 ...
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... Speed Selection: This bit determines the speed of operation of the 78Q2123/78Q2133. Setting this bit to ‘1’ indicates 100Base-TX operation and a ‘0’ indicates 10Base-T mode. This bit will default to a ‘1’ upon reset. When auto-negotiation is enabled, this bit will not be writable and will have no effect on the 78Q2123/78Q2133 ...
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... Data Sheet 3.2 MR1: Status Register Bits 1.15 through 1.11 reflect the ability of the 78Q2123/78Q2133. They do not reflect any ability changes made via the MII Management Interface to bits 0.13 (SPEEDSL) , 0.12 (ANEGEN) and 0.8 (DUPLEX) in the Control Register. Bit Symbol ...
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... Organizationally Unique Identifier: Remaining 6 bits of the OUI. 23h Model Number: The last 2 digits of the model number 78Q2123 are encoded into the 6 bits for both 78Q2123 and 78Q2133. 07h Revision Number: The value ‘0111’ corresponds to the seventh revision of the silicon. ...
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... Link Partner Next Page Able: When ‘1’ is read, it indicates the link partner supports the Next Page function. 0 Next Page Able: Reads ‘0’ since the 78Q2123/78Q2133 do not support Next Page function. 0 Page Received: Reads ‘1’ when a new link code word has been received into the Auto-Negotiation Link Partner Ability Register ...
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... Reserved 1 Reserved 0 Auto Polarity: During auto-negotiation and 10BASE-T mode, the 78Q2123/78Q2133 are able to automatically invert the received signal due to a wrong polarity connection. It does so by detecting the polarity of the link pulses. Setting this bit to ‘1’ disables this feature. 0 Reverse Polarity: The reverse polarity is detected either ...
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... Data Sheet 3.9 MR17: Interrupt Control/Status Register The Interrupt Control/Status Register provides the means for controlling and observing the events, which trigger an interrupt on the INTR pin. This register can also be used in a polling mode via the MII Serial Interface as a means to observe key events within the PHY via one register address. Bits 0 through 7 are status bits, which are each set to logic one based upon an event ...
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... Gain set for 0.4dB of insertion loss Gain set for 0.8dB of insertion loss Gain set for 1.2dB of insertion loss. XXXh Reserved Default Description XXXXh Reserved: must be 0000h. Default Description XXXXh Reserved: must be 0000h. Default Description XXXXh Reserved: must be 0000h. 78Q2123/78Q2133 Data Sheet 21 ...
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... Data Sheet 3.15 MR23: LED Configuration Register Bit Symbol Type 23.15:8 Reserved NA 23.7:4 LED1[3:0] R/W 23.3:0 LED0[3:0] R/W 3.16 MR24: MDI/MDIX Control Register Bit Symbol Type 24.15:8 Reserved R 24.7 PD_MODE R/W 24.6 AUTO_SW R/W 24.5 MDIX R/W 24.4 MDIX_CM R 24.3:0 ...
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... Pin Current 4.2 Recommended Operating Conditions Unless otherwise noted, all specifications are valid over these temperatures and supply voltage ranges. Parameter DC Voltage Supply (Vcc) 78Q2123 Ambient Operating Temperature (Ta) 78Q2133 Ambient Operating Temperature (Ta) Maximum Junction Temperature Package Thermal Conductivity (θja) 4.3 DC Characteristics ...
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... Data Sheet 4.4 Digital I/O Characteristics Pins of type CI, CIU, CID, CIO Parameter Symbol Input Voltage Low Vil Input Voltage High Vih Input Current Iil, Iih Pull-up Resistance Rpu Input Capacitance Cin Pins of type CIS Parameter Symbol Low-to-High Threshold Vt+ High-to-Low Threshold ...
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... Characteristics Symbol Setup Time: TX_CLK to TX TXD[3:0], TX_EN, TX_ER Hold Time: TX_CLK to TX TXD[3:0], TX_EN, TX_ER CKIN-to-TX_CLK Delay T TX_CLK Duty-Cycle Figure 2: Transmit Inputs to the 78Q2123/78Q2133 Rev. 1.6 T reset Figure 1: RST Pulse Duration Conditions VCC = 3.3V and oscillator stabilized Conditions SU HD CKIN ...
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... Figure 3: Receive Outputs from the 78Q2123/78Q2133 4.6 MDIO Interface Input Timing Characteristics Symbol Setup Time: MDC to MDIO MIO Hold Time: MDC to MDIO MIO Max Frequency: MDC F Figure 4: MDIO as an Input to the 78Q2123/78Q2133 26 Conditions DLY Conditions SU HD max DS_21x3_001 Min Nom Max ...
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... MDIO Interface Output Timing Characteristics Symbol MDC to MDIO data delay MC2D MDIO output from high Z MCZ2D to driven after MDC MDIO output from driven MCD2Z to high Z after MDC Figure 5: MDIO as an Output to the 78Q2123/78Q2133 Rev. 1.6 78Q2123/78Q2133 Data Sheet Conditions Min Nom Max Unit ...
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... Data Sheet 4.6.2 MDIO Interface Output Timing 28 Figure 6: MDIO Interface Output Timing DS_21x3_001 Rev. 1.6 ...
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... RD to RXD at (MII) Delay Collision delay SQE test wait SQE test duration Jabber on-time* Jabber off-time* * Guarantee by design. The specifications in the following table are included for information only. Rev. 1.6 Condition RPTR = low RPTR = low Condition Min 20 250 78Q2123/78Q2133 Data Sheet Nom Unit ...
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... Data Sheet 4.7 Analog Electrical Characteristics 4.7.1 100BASE-TX Transmitter Parameter Peak Output Amplitude Best-fit over 14 bit times; (|Vp+|, |Vp-|) 0.4 dB Transformer loss (see note below) Output Amplitude |Vp +| Symmetry |Vp -| Output Overshoot Percent of Vp+, Vp- Rise/Fall time (tr, tf) 10-90% of Vp+, Vp- Rise/Fall time Imbalance |tr - tf| ...
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... MHz sine wave pk applied to transmitter common-mode. All data sequences 10.1 MHz sine wave pk applied to transmitter common-mode. All data sequences. Condition Square wave 0 < f < 500 kHz Not tested 78Q2123/78Q2133 Data Sheet Min Nom Max 2.2 2.8 27 100 300 350 Min Nom Max 15 ...
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... TX_CLK VCC 16 25 TX_EN XTLN Y 1 25.000MHz C13 C14 27pF 27pF VCC C15 R24 C13 and C14 must be calibrated 10k in actual application board for 0.1uF 25.000MHz +/-50ppm. Figure 7: Application Diagram for 78Q2123/78Q2133 VCC R8 R9 VCC 49.9 49 0.01uF 0.1uF TD+ TX TDCT TXCT ...
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... Vrms Value 25.00000 4** ±50 ±2 ±5 Parallel Resonance, Fundamental Mode 50-100 > below main within 500 kHz 78Q2123/78Q2133 Data Sheet Condition @ 10 mV, 10 kHz @ 1 MHz (min MHz Units MHz pF PPM PPM/yr PPM µ Ω 33 ...
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... Data Sheet Figure 8: External XTLP Oscillator Characteristics 4.9.1 External XTLP Oscillator Characteristics Parameter Symbol XTLP Input Level XTLN Input Low Voltage XTLP Frequency f XTLP Period Tclkper XTLP Duty Cycle Rise / Fall Time Tr, Tf Absolute Jitter Note 1: IEEE 802.3 frequency tolerance ±50 ppm. ...
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... MDC LED1 LED0 RXD3 RXD2 RXD1 RXD0 Note: For information only, actual package outline will vary depending on package type. Rev. 1 TERIDIAN 4 78Q2123 5 78Q2133 Figure 9: Package Pin Designations 78Q2123/78Q2133 Data Sheet 24 XTLP RST 23 22 CRS COL 21 20 TXD3 19 TXD2 18 TXD1 TXD0 17 35 ...
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... Data Sheet 6 32-Pin QFN Mechanical Specifications Dimensions in mm TOP VIEW 0.2 MIN. 0.35 / 0.45 Figure 10: 32-Pin QFN Mechanical Specifications 36 / 0.85 NOM. 0.9MAX. 2.5 3.0 / 3.2 0.18 / 0.3 1.5 / 1.6 0.5 BOTTOM VIEW DS_21x3_001 0.00 / 0.005 0.20 REF. SEATING PLANE SIDE VIEW CHAMFERED 0 ...
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... Lead-Free 32-QFN, Industrial Temp, Tape and Reel Rev. 1 Min Lead pitch See Note 1 3.93 mm Order Number 78Q2123/F 78Q2123R/F 78Q2133/F 78Q2133R/F 78Q2123/78Q2133 Data Sheet Typ Max 0.50 mm 0.28 mm 0.28 mm 0.69 mm 3.00 mm 3.78 mm Package Mark 78Q2123 xxxxxP7F 78Q2123 xxxxxP7F 78Q2133 xxxxxP7F 78Q2133 ...
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... Data Sheet Revision History Rev. # Date 1.0 9/15/2005 1.6 4/16/2010 Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. MicroDAA is a registered trademark of Teridian Semiconductor Corporation. All other trademarks are the property of their respective owners. ...