KSZ8851-16MLLU TR Micrel, KSZ8851-16MLLU TR Datasheet - Page 8

• Manufacturer Part Number: KSZ8851-16MLLU TR
• Description: Ethernet ICs Single-Port Ethernet Controller (Automotive Grade)
• Manufacturer: Micrel

Specifications of KSZ8851-16MLLU TR

• Rohs: yes
• Product: Ethernet Controllers
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

Micrel, Inc.
KSZ8851-16MLL/MLLI
List of Figures
Figure 1. KSZ8851-16MLL/MLLI Functional Diagram ............................................................................................................ 1
Figure 2. 48-Pin LQFP ......................................................................................................................................................... 10
Figure 3. Typical Straight Cable Connection ........................................................................................................................ 20
Figure 4. Typical Crossover Cable Connection .................................................................................................................... 21
Figure 5. Auto Negotiation and Parallel Operation ............................................................................................................... 22
Figure 6. KSZ8851-16MLL 8-Bit and 16-Bit Data Bus Connections..................................................................................... 27
Figure 7. Host TX Single Frame in Manual Enqueue Flow Diagram .................................................................................... 30
Figure 8. Host TX Multiple Frames in Auto- Enqueue Flow Diagram ................................................................................... 30
Figure 8. Host TX Multiple Frames in Auto- Enqueue Flow Diagram ................................................................................... 31
Figure 9. Host RX Single or Multiple Frames in Auto-Dequeue Flow Diagram .................................................................... 33
Figure 10. PHY Port 1 Near-end (Remote) and Host Far-end (Local) Loopback Paths....................................................... 35
Figure 11. Asynchronous Cycle ............................................................................................................................................ 75
Figure 12. Auto Negotiation Timing ...................................................................................................................................... 76
Figure 13. Reset Timing........................................................................................................................................................ 77
Figure 14. EEPROM Read Cycle Timing Diagram ............................................................................................................... 78
Figure 15. Recommended Reset Circuit.............................................................................................................................. 79
Figure 16. Recommended Circuit for Interfacing with CPU/FPGA Reset............................................................................ 79
Figure 17. 48-Pin (7mm x 7mm) LQFP................................................................................................................................ 81
May 2012
8
M9999-050112-2.1