KSZ8851-16MLLU TR Micrel, KSZ8851-16MLLU TR Datasheet - Page 55

• Manufacturer Part Number: KSZ8851-16MLLU TR
• Description: Ethernet ICs Single-Port Ethernet Controller (Automotive Grade)
• Manufacturer: Micrel

Specifications of KSZ8851-16MLLU TR

• Rohs: yes
• Product: Ethernet Controllers
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

TXQ Command Register (0x80 – 0x81): TXQCR
This register is programmed by the Host CPU to issue a transmit command to the TXQ. The present transmit frame in
the TXQ memory is queued for transmit.
RXQ Command Register (0x82 – 0x83): RXQCR
This register is programmed by the Host CPU to issue DMA read or write command to the RXQ and TXQ. This register
also is used to control all RX thresholds enable and status.
May 2012
Micrel, Inc.
Bit
15-2
1
0
Bit
15-13
12
11
10
9
8
7
6
5
Default Value
Default Value
0x0
0x0
0x0
0x0
0x0
0x0
-
-
-
-
-
-
R/W
RW
RW
RW
RW
RW
RW
RO
RO
RO
R/W
RW
RW
RW
Description
Reserved.
RXDTTS RX Duration Timer Threshold Status
When this bit is set, it indicates that RX interrupt is due to the time start at first received frame in
RXQ buffer exceeds the threshold set in RX Duration Timer Threshold Register (0x8C,
RXDTT).
This bit will be uPDated when write 1 to bit 13 in ISR register.
RXDBCTS RX Data Byte Count Threshold Status
When this bit is set, it indicates that RX interrupt is due to the number of received bytes in RXQ
buffer exceeds the threshold set in RX Data Byte Count Threshold Register (0x8E, RXDBCT).
This bit will be uPDated when write 1 to bit 13 in ISR register.
RXFCTS RX Frame Count Threshold Status
When this bit is set, it indicates that RX interrupt is due to the number of received frames in
RXQ buffer exceeds the threshold set in RX Frame Count Threshold Register (0x9C, RXFCT).
This bit will be uPDated when write 1 to bit 13 in ISR register.
RXIPHTOE RX IP Header Two-Byte Offset Enable
When this bit is written as 1, the KSZ8851-16MLL will enable to add two bytes before frame
header in order for IP header inside the frame contents to be aligned with double word
boundary to speed up software operation.
Reserved.
RXDTTE RX Duration Timer Threshold Enable
When this bit is written as 1, the KSZ8851-16MLL will enable RX interrupt (bit 13 in ISR) when
the time start at first received frame in RXQ buffer exceeds the threshold set in RX Duration
Timer Threshold Register (0x8C, RXDTT).
RXDBCTE RX Data Byte Count Threshold Enable
When this bit is written as 1, the KSZ8851-16MLL will enable RX interrupt (bit 13 in ISR) when
the number of received bytes in RXQ buffer exceeds the threshold set in RX Data Byte Count
Threshold Register (0x8E, RXDBCT).
RXFCTE RX Frame Count Threshold Enable
When this bit is written as 1, the KSZ8851-16MLL will enable RX interrupt (bit 13 in ISR) when
the number of received frames in RXQ buffer exceeds the threshold set in RX Frame Count
Threshold Register (0x9C, RXFCT).
Description
Reserved
TXQMAM TXQ Memory Available Monitor
When this bit is written as 1, the KSZ8851-16MLL will generate interrupt (bit 6 in ISR
register) to CPU when TXQ memory is available based upon the total amount of TXQ space
requested by CPU at TXNTFSR (0x9E) register.
Note: This bit is self-clearing after the frame is finished transmitting. The software should
wait for the bit to be cleared before set to 1 again.
METFE Manual Enqueue TXQ Frame Enable
When this bit is written as 1, the KSZ8851-16MLL will enable current TX frame prepared in
the TX buffer is queued for transmit, this is only transmit one frame at a time.
Note: This bit is self-clearing after the frame is finished transmitting. The software should
wait for the bit to be cleared before setting up another new TX frame.
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KSZ8851-16MLL/MLLI
M9999-050112-2.1