KSZ8041TLI-S Micrel, KSZ8041TLI-S Datasheet - Page 24

• Manufacturer Part Number: KSZ8041TLI-S
• Description: Ethernet ICs Physical Layer Transceiver 10/100BASE-FX (Lead Free)
• Manufacturer: Micrel

Specifications of KSZ8041TLI-S

• Rohs: yes
• Product: Ethernet Transceivers
• Package / Case: TQFP-48
• Mounting Style: SMD/SMT

Micrel, Inc.
Collision Detection
The MAC regenerates the COL signal of the MII from TX_EN and CRS_DV.
Serial MII (SMII) Data Interface
The Serial Media Independent Interface (SMII) is the lowest pin count Media Independent Interface (MII). It provides a
common interface between physical layer and MAC layer devices, and has the following key characteristics:
The KSZ8041TL/FTL is configured in SMII mode after it is power-up or reset with the following:
In SMII mode, unused MII signals, TXD[3:2] (pins 39, 38), are tied to ground.
SMII Signal Definition
The following table describes the SMII signals. Refer to SMII Specification for detailed information.
Clock Reference (CLOCK)
CLOCK is sourced by the MAC or system board. It is a continuous 125 MHz clock that provides the timing reference for
SYNC, TX, and RX.
Sync Pulse (SYNC)
SYNC is a 12.5 MHz synchronized pulse derived from CLOCK by the MAC. It is used to indicate the segment boundary
for each transmit data/control segment, or receive data/control segment. Each segment is comprised of ten bits.
SYNC is generated continuously by the MAC at every ten cycles of CLOCK.
Transmit Data and Control (TX)
TX provides transmit data and control information from MAC-to-PHY in 10-bit segments.
April 2007
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Supports 10Mbps and 100Mbps data rates.
Uses 125 MHz reference clock provided by the MAC or the system board.
Uses 12.5 MHz sync pulse provided by the MAC.
Provides independent single-bit wide transmit and receive data paths for data and control information.
A 125 MHz reference clock connected to CLOCK (pin 15).
A 12.5 MHz sync pulse connected to SYNC (pin 36).
CONFIG[2:0] (pins 27, 41, 40) set to ‘010’.
In 10Mbps mode, each segment is repeated ten times. Therefore, every ten segments represent a new byte of
data. The PHY can sample any one of every ten segments.
In 100Mbps mode, each segment represents a new byte of data.
SMII
Signal Name
CLOCK
SYNC
TX
RX
Direction
(with respect to PHY,
KSZ8041TL/FTL signal)
Input
Input
Input
Output
Table 4. SMII Signal Description
Direction
(with respect to MAC)
Input, or Output
Output
Output
Input
24
Description
125 MHz clock reference for receive and
transmit data and control
12.5 MHz sync pulse from MAC
Transmit Data and Control
Receive Data and Control
M9999-042707-1.1
KSZ8041TL/FTL