KSZ8041TLI-S Micrel, KSZ8041TLI-S Datasheet - Page 10

• Manufacturer Part Number: KSZ8041TLI-S
• Description: Ethernet ICs Physical Layer Transceiver 10/100BASE-FX (Lead Free)
• Manufacturer: Micrel

Specifications of KSZ8041TLI-S

• Rohs: yes
• Product: Ethernet Transceivers
• Package / Case: TQFP-48
• Mounting Style: SMD/SMT

Micrel, Inc.
Pin Description
April 2007
Pin Number
10
11
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
VDDA_1.8
VDDA_1.8
V1.8_OUT
VDDA_3.3
VDDA_3.3
Pin Name
REFCLK /
PHYAD0
PHYAD1
PHYAD2
RXD[1] /
CLOCK
RXD3 /
RXD2 /
RXD1 /
REXT
MDIO
MDC
GND
GND
GND
GND
GND
RX+
TX+
RX-
TX-
XI /
XO
Type
Ipu/O
Ipd/O
Ipd/O
Gnd
Gnd
Gnd
Gnd
Gnd
I/O
I/O
I/O
I/O
I/O
I/O
O
P
P
P
P
P
I
I
(1)
Pin Function
Ground
Ground
Ground
1.8V analog V
1.8V analog V
1.8V output voltage from chip
3.3V analog V
3.3V analog V
Physical receive or transmit signal (- differential)
Physical receive or transmit signal (+ differential)
Physical transmit or receive signal (- differential)
Physical transmit or receive signal (+ differential)
Ground
Crystal feedback
This pin is used only in MII mode when a 25 MHz crystal is used.
This pin is a no connect if oscillator or external clock source is used, or if RMII
mode or SMII mode is selected.
Crystal / Oscillator / External Clock Input
MII Mode:
RMII Mode:
SMII Mode:
Set physical transmit output current
Connect a 6.49KΩ resistor in parallel with a 100pF capacitor to ground on this
pin. See KSZ8041TL-FTL reference schematics.
Ground
Management Interface (MII) Data I/O
This pin requires an external 4.7KΩ pull-up resistor.
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
MII Mode:
Config Mode:
MII Mode:
Config Mode:
MII Mode:
RMII Mode:
Config Mode:
DD
DD
DD
DD
25MHz +/-50ppm (crystal, oscillator, or external clock)
50MHz +/-50ppm (oscillator, or external clock only)
125MHz +/-100ppm (oscillator, or external clock only)
Receive Data Output[3]
The pull-up/pull-down value is latched as PHYADDR[0] during
power-up / reset. See “Strapping Options” section for details.
Receive Data Output[2]
The pull-up/pull-down value is latched as PHYADDR[1] during
power-up / reset. See “Strapping Options” section for details.
Receive Data Output[1]
Receive Data Output[1]
The pull-up/pull-down value is latched as PHYADDR[2] during
power-up / reset. See “Strapping Options” section for details.
10
(2)
(2)
(2)
(3)
/
/
/
/
KSZ8041TL/FTL
M9999-042707-1.1