1893Y-10LFT IDT, 1893Y-10LFT Datasheet - Page 129
![no-image](/images/no-image-200.jpg)
1893Y-10LFT
Manufacturer Part Number
1893Y-10LFT
Description
Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
Manufacturer
IDT
Datasheet
1.1893Y-10LFT.pdf
(152 pages)
Specifications of 1893Y-10LFT
Rohs
yes
Part # Aliases
ICS1893Y-10LFT
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10.5.3 Timing for Receive Clock (RXCLK) Pins
ICS1893 Rev C 6/6/00
Table 10-10
interfaces.
Table 10-10. MII Receive Clock Timing
Figure 10-4. Receive Clock Timing Diagram
RXCLK
Period
Time
t2a
t2b
t2c
t2d
ICS1893 - Release
t1
RXCLK Duty Cycle
RXCLK Period
RXCLK Period
RXCLK Period
RXCLK Period
Figure 10-4
lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various
Parameter
shows the timing diagram for the time periods.
t1
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
t2
100M MII (100Base-TX)
10M MII (10Base-T)
100M Symbol Interface (100Base-TX)
10M Serial Interface (10Base-T)
129
Conditions
–
Chapter 10 DC and AC Operating Conditions
Min. Typ. Max.
35
–
–
–
–
400
100
50
40
40
65
–
–
–
–
June, 2000
Units
ns
ns
ns
ns
%
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