1893Y-10 IDT, Integrated Device Technology Inc, 1893Y-10 Datasheet
1893Y-10
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... ICS1892. The ICS1893 supports managed or unmanaged node, repeater, and switch applications. The ICS1893 incorporates digital signal processing (DSP) in its Physical Medium Dependent (PMD) sublayer result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cables with attenuation in excess 100 MHz. With this ICS-patented technology, the ICS1893 can virtually eliminate errors from killer packets ...
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ICS1893 Data Sheet - Release Section Revision History ............................................................................................................................. 9 Chapter 1 Abbreviations and Acronyms ......................................................................................... 11 Chapter 2 Conventions and Nomenclature..................................................................................... 13 Chapter 3 ICS1893 Enhanced Features ........................................................................................... 15 Chapter 4 Overview of the ICS1893.................................................................................................. 17 4.1 100Base-TX Operation ...
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ICS1893 - Release Section 7.3 Functional Block: 100Base-X PCS and PMA Sublayers ........................................ 44 7.3.1 PCS Sublayer ........................................................................................................ 44 7.3.2 PMA Sublayer ........................................................................................................ 44 7.3.3 PCS/PMA Transmit Modules ................................................................................. 45 7.3.4 PCS/PMA Receive Modules .................................................................................. 46 7.3.5 PCS Control Signal ...
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... Auto-Negotiation Ability (bit 1.3) ............................................................................ 70 8.3.11 Link Status (bit 1.2) ................................................................................................ 71 8.3.12 Jabber Detect (bit 1.1) ........................................................................................... 71 8.3.13 Extended Capability (bit 1.0) .................................................................................. 71 8.4 Register 2: PHY Identifier Register ........................................................................ 72 ICS1893 Rev C 6/6/00 Table of Contents Title Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 4 Table of Contents ...
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... ICS1893 - Release Section 8.5 Register 3: PHY Identifier Register ........................................................................ 74 8.5.1 OUI bits 19-24 (bits 3.15:10) .................................................................................. 74 8.5.2 Manufacturer's Model Number (bits 3.9:4) ............................................................. 75 8.5.3 Revision Number (bits 3.3:0) ................................................................................. 75 8.6 Register 4: Auto-Negotiation Register ................................................................... 76 8.6.1 Next Page (bit 4.15) ............................................................................................... 76 8.6.2 IEEE Reserved Bit (bit 4.14) .................................................................................. 77 8.6.3 Remote Fault (bit 4 ...
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... Register 16: Extended Control Register ................................................................ 88 8.11.1 Command Override Write Enable (bit 16.15) ......................................................... 89 8.11.2 ICS Reserved (bits 16.14:11) ................................................................................. 89 8.11.3 PHY Address (bits 16.10:6) ................................................................................... 89 8.11.4 Stream Cipher Scrambler Test Mode (bit 16.5) ..................................................... 89 8.11.5 ICS Reserved (bit 16.4) ......................................................................................... 89 8.11.6 NRZ/NRZI Encoding (bit 16.3) ............................................................................... 89 8.11.7 Invalid Error Code Test (bit 16 ...
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... ICS1893 Pin Diagram .......................................................................................... 103 9.2 ICS1893 Pin Listings ............................................................................................ 104 9.3 ICS1893 Pin Descriptions .................................................................................... 105 9.3.1 Transformer Interface Pins .................................................................................. 105 9.3.2 Multi-Function (Multiplexed) Pins: PHY Address and LED Pins .......................... 106 9.3.3 Configuration Pins ................................................................................................ 110 9.3.4 MAC/Repeater Interface Pins .............................................................................. 112 9.3.5 Reserved Pins ...................................................................................................... 121 9.3.6 Ground and Power Pins ...
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... Jabber Timing ..................................................................................... 146 10.5.21 10Base-T: Normal Link Pulse Timing .................................................................. 147 10.5.22 Auto-Negotiation Fast Link Pulse Timing ............................................................. 148 Chapter 11 Physical Dimensions of ICS1893 Package................................................................ 149 Chapter 12 Ordering Information ................................................................................................... 151 ICS1893 Rev C 6/6/00 Table of Contents Title Copyright © 2000, Integrated Circuit Systems, Inc. ...
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... Table 10-28. Changes to table values. – Table 10-29. Changes to table values. – Chapter 11, “ Physical Dimensions of ICS1893 Package” ICS1893 Rev C 6/6/00 . Change to text in 1(a). . New paragraph. (Subsequent paragraphs reflect . ICS1893 pin names have changes. . Changes to text in bullets. Copyright © 2000, Integrated Circuit Systems, Inc. ...
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ICS1893 Data Sheet - Release • This release of this document, Rev C, is dated May 22, 2000. Change bars indicate where all changes are made. (For an explanation of change bars, see the Change Bar note on this page.) ...
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ICS1893 - Release Chapter 1 Abbreviations and Acronyms Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet. Table 1-1. Abbreviations and Acronyms Abbreviation / Acronym 4B/5B 4-Bit / 5-Bit Encoding/Decoding ANSI American National Standards Institute ...
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... Acronym OUI Organizationally Unique Identifier PCS Physical Coding sublayer PHY physical-layer device The ICS1893 is a physical-layer device, also referred ‘ PHY’ or ‘ PHYceiver’ . (The ICS1890 is also a physical-layer device.) PLL phase-locked loop PMA Physical Medium Attachment PMD Physical Medium Dependent ...
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ICS1893 - Release Chapter 2 Conventions and Nomenclature Table 2-1 lists and explains the conventions and nomenclature used throughout this data sheet. Table 2-1. Conventions and Nomenclature Item Bits Code groups Colon (:) Numbers Pin (or signal) names Registers ICS1893 ...
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ICS1893 Data Sheet - Release Table 2-1. Conventions and Nomenclature (Continued) Item Signal references Symbols Terms: ‘ set’ , ‘ active’ , ‘ asserted’ , Terms: ‘ cleared’ , ‘ de-asserted’ , ‘ inactive’ Terms: ‘ twisted-pair receiver’ Terms: ‘ ...
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... The ICS1893 employs an advanced digital signal processing (DSP) architecture that improves the 100Base-TX Receiver performance beyond that of any other PHY in the market. Specifically: a. The ICS1893 DSP-based, adaptive equalization process allows the ICS1893 to accommodate a maximum cable attenuation/insertion loss in excess of 24 dB, which is nearly equivalent to the attenuation loss of a 100-meter Category 5 cable ...
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ICS1893 Data Sheet - Release Table 3-1. Summary of Differences between ICS1890 and ICS1893 Registers Register. ICS1890 Bit(s) Function 1.6 Reserved 3.9:4 Model Number 3.3:0 Revision Number 6.2 Next Page Able 7.15:0 Not applicable (N/A) 8.15:0 N/A 9.15:0 IEEE reserved. ...
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... ICS1893 converts and decodes a serial bit stream (acquired from an isolation transformer that interfaces with the medium) into sequential nibbles. It subsequently presents these nibbles to its MAC/Repeater Interface. The ICS1893 implements the OSI model’ s physical layer, consisting of the following, as defined by the ISO/IEC 8802-3 standard: • ...
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... For 100M data transmission, the ICS1893 MAC/Repeater Interface can be configured to provide either a 100M Media Independent Interface (MII 100M Symbol Interface. With the Symbol Interface configuration, the data stream bypasses the ICS1893 Physical Coding sublayer (PCS). In addition: 1. The ICS1893 shifts the responsibility of performing the 4B/5B translation to the MAC/repeater result, the requirement is for a 5-bit data path between the MAC/repeater and the ICS1893 ...
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ICS1893 - Release Chapter 5 Operating Modes Overview The ICS1893 operating modes and interfaces are configurable with one of two methods. The HW/SW (hardware/software) pin determines which method the ICS1893 is to use, either its hardware pins or its register ...
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... Latches the Serial Management Port Address of the ICS1893 into the Extended Control Register, bits 16.10:6. [See Section 8.11.3, “ PHY Address (bits 16.10:6)” 3. Enables all its internal modules and state machines 4. Sets all Management Register bits to either (1) their default values or (2) the values specified by their associated ICS1893 input pins, as determined by the HW/SW pin 5 ...
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ICS1893 - Release 5.1.2 Specific Reset Operations This section discusses the following specific ways that the ICS1893 can be reset: • Hardware reset (using the RESETn pin) • Power-on reset (applying power to the ICS1893) • Software reset (using Control ...
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... Address into the Extended Control Register. [For information on the Serial Management Port Address, see Section 8.11.3, “ PHY Address (bits 16.10:6)” 3. The Control Register bit 0.15 does not represent the status of a hardware reset self-clearing bit that is used to initiate a software reset. During a hardware or power-on reset, Control Register bit 0.15 does not get set to logic one ...
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ICS1893 - Release 5.3 Automatic Power-Saving Operations The ICS1893 has power-saving features that automatically minimize its total power consumption while it is operating. Table 5-1 lists the ICS1893 automatic power-saving features for the various modes. Table 5-1. Automatic Power-Saving Features, ...
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... Link Segment throughput to either 20 Mbps (for 10Base-T operations) or 200 Mbps (for 100Base-TX operations). As per the ISO/IEC standard, full-duplex operations differ slightly from half-duplex operations. These differences are necessary, as during full-duplex operations a PHY actively uses both its transmit and receive data paths simultaneously. • ...
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... ICS1893 - Release Chapter 6 Interface Overviews The ICS1893 MAC/Repeater Interface is fully configurable, thereby allowing it to accommodate many different applications. This chapter includes overviews of the following MAC/repeater-to-PHY interfaces: • Section 6.1, “ MII Data Interface” • Section 6.2, “ 100M Symbol Interface” ...
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... The most common configuration for an ICS1893’ s MAC/Repeater Interface is the Medium Independent Interface (MII) operating at either 10 Mbps or 100 Mbps. When the ICS1893 MAC/Repeater Interface is configured for the MII Data Interface mode, data is transferred between the PHY and the MAC/repeater as framed, 4-bit parallel nibbles. In addition, the interface also provides status and control signals to synchronize the transfers ...
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... PHY. That is, when the ICS1893’ s MAC/Repeater Interface is configured as a 100M Symbol Interface, the bit delays through the PHY are smaller than the standard MII Data Interface can allow. The ICS1893 provides this 100M Symbol Interface primarily for Repeater applications, for which latency is a critical performance parameter ...
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... MDIO RXCLK SRCLK RXD0 SRD0 RXD1 SRD1 RXD2 SRD2 RXD3 SRD3 RXDV No connect. (Data exchanged between the MAC/repeater and a PHY is not framed in the 100M Symbol Interface mode. Therefore, RXDV has no meaning.) RXER SRD4 TXCLK STCLK TXD0 STD0 TXD1 STD1 TXD2 STD2 ...
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ICS1893 - Release 6.3 10M Serial Interface When the Mac/Repeater Interface is configured as a 10M Serial Interface, the ICS1893 and the MAC/repeater exchange a framed, serial bit stream along with associated control signals. The 10M Serial Interface configuration is ...
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ICS1893 Data Sheet - Release Table 6-2 lists the pin mappings for the ICS1893 10M Serial Interface mode. Table 6-2. Pin Mappings for 10M Serial Interface Mode Default 10M / 100M MII Pin Names COL 10COL CRS 10CRS MDC MDC ...
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... ICS1893. The ISO/IEC standard also specifies a frame structure and protocol for this interface as well as a set of Management Registers that provide the STA with access to a PHY such as the ICS1893. A Serial Management Interface is comprised of two signals: a bi-directional data pin (MDIO) along with an associated input pin for a clock (MDC) ...
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ICS1893 Data Sheet - Release 6.5.1 Twisted-Pair Transmitter Interface The twisted-pair transmitter driver uses an H-bridge configuration, which requires that the transmit transformer not have a choke on the chip side. ICS suggests any of the following for the H-bridge: ...
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ICS1893 - Release 6.5.2 Twisted-Pair Receiver Interface Figure 6-2 shows the design for the ICS1893 twisted-pair receiver interface. • Two 56.2 1% resistors are in series, with the center bypassed to ground with a 0.1- F bypass capacitor. • No ...
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ICS1893 Data Sheet - Release 6.6 Clock Reference Interface The REF_IN pin provides the ICS1893 Clock Reference Interface. The ICS1893 requires a single clock reference with a frequency of 25 MHz ±50 parts per million. This accuracy is necessary to ...
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... Adding 10K resistors across the LEDs ensures the PHY address is fully defined during slow VDD power-ramp conditions. 6. PHY address 00 tri-states the MII interface. (Do not select PHY address 00 unless you want the MII tri-stated.) ICS1893 Rev C 6/6/00 6-3, the ICS1893 provides five multi-function configuration pins that report the Copyright © ...
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... TRANS 10K 10K This circuit decodes to PHY address = 1. Note: 1. All LED pins must be set during reset. 2. PHY address 00 tri-states the MII interface. 3. For more reliable address capture during power-on reset, add a 10K resistor across the LED. ICS1893 Rev C 6/6/00 ICS1893 P2LI ...
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ICS1893 - Release Chapter 7 Functional Blocks This chapter discusses the following ICS1893 functional blocks. • Section 7.1, “ Functional Block: Media Independent Interface” • Section 7.2, “ Functional Block: Auto-Negotiation” • Section 7.3, “ Functional Block: 100Base-X PCS and ...
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... ICS1893 MIIs can support two data transfer rates: 25 MHz (for 100Base-TX operations) and 2.5 MHz (for 10Base-T operations). The Media Independent Interface (MII) consists of two primary components interface between a MAC (Media Access Control sublayer) and the PHY (that is, the ICS1893). This MAC-PHY part of the MII consists of three subcomponents synchronous Transmit interface that includes the following signals: ...
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ICS1893 - Release 7.2 Functional Block: Auto-Negotiation The auto-negotiation logic of the ICS1893 has the following main functions: • To determine the capabilities of the remote link partner, (that is, the device at the other end of the link segment’ ...
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... ICS1893 Data Sheet - Release 7.2.1 Auto-Negotiation General Process The Auto-Negotiation sublayer uses a physical signaling technique that is transparent at the packet level and all higher protocol levels. This technique builds on the link pulse mechanism employed in 10Base-T operations and is fully compliant with clause 28 of the ISO/IEC 8802-3 standard. ...
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ICS1893 - Release 7.2.2 Auto-Negotiation: Parallel Detection The ICS1893 supports parallel detection therefore compatible with networks that do not support the auto-negotiation process. When enabled, the Auto-Negotiation sublayer can detect legacy 10Base-T link partners as well as 100Base-TX ...
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ICS1893 Data Sheet - Release 7.2.4 Auto-Negotiation: Reset and Restart If enabled, execution of the ICS1893 auto-negotiation process occurs at power-up and upon management request. There are two primary ways to begin the Auto-Negotiation state machine: • ICS1893 reset • ...
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ICS1893 - Release Auto-Negotiation Link Partner Ability Register and determine the highest-performance operating mode in common with the capabilities it is advertising. The ISO/IEC-defined priority table determines the established link type simpler alternative, the STA can read the ...
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... Receive modules are inactive. However, its PCS control functions (CRS and COL) remain operational. 7.3.2 PMA Sublayer The ICS1893 100Base-X PMA Sublayer consists of two interfaces: one to the Physical Coding sublayer and the other to the Physical Medium Dependent sublayer. Functionally, the PMA sublayer is responsible for the following: • Link Monitoring • ...
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... PMA Transmit Module The ICS1893 PMA Transmit module accepts a serial bit stream from its PCS and converts the data into NRZI format. Subsequently, the PMA passes the NRZI bit stream to the Twisted-Pair Physical Medium Dependent (TP-PMD) sublayer. The ICS1893 PMA Transmit module uses a digital PLL to synthesize a transmit clock from the Clock Reference Interface. When the ICS1893 is configured for an interface that is: • ...
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... NRZI Decoding The Receive module performs the NRZI decoding on the serial bit stream received from the Twisted-Pair Physical Medium Dependent (TP-PMD) sublayer. It converts the bit stream to a unipolar, positive, binary format that the PMA subsequently passes to the PCS. • Receive Clock Recovery The Receive Clock Recovery function consists of a phase-locked loop (PLL) that operates on the serial data stream received from the PMD sublayer ...
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ICS1893 - Release 7.3.5 PCS Control Signal Generation For the PCS sublayer, there are two control signals: a Carrier Sense signal (CRS) and a Collision Detect signal (COL). The CRS control signals is generated as follows: 1. When a logic ...
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... TP-PMD module performs stream-cipher scrambling/descrambling and MLT-3 encoding/decoding (3-level, multi-level transition) in compliance with the ANSI Standard X3.263: 199X FDDI TP-PMD as defined in the specification for 100Base-TX Twisted-Pair Physical Media Dependent (TP-PMD) Sublayer. The ICS1893’ s TP-PMD also performs DC restoration (that is, baseline wander correction) and adaptive equalization on the received signals ...
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ICS1893 - Release 7.4.4 100Base-TX Operation: Adaptive Equalizer The ICS1893 has a TP-PMD sublayer that uses adaptive equalization circuitry to compensate for signal amplitude and phase distortion incurred from the transmission medium data rate of 100 Mbps, the ...
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... The ICS1893 interfaces with a medium through isolation transformers. The PHY requires two isolation transformers: one for its Twisted-Pair Transmitter and the other for its Twisted-Pair Receiver. These isolation transformers provide both physical isolation as well as the means for coupling a signal between the ICS1893 and the medium for both 10Base-T and 100Base-TX operations. ...
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ICS1893 - Release 7.5 Functional Block: 10Base-T Operations When configured for 10Base-T mode, the ICS1893 MAC/Repeater Interface can be configured to provide either a 10M MII (Media Independent Interface 10M Serial Interface. The Twisted-Pair Interface is automatically configured ...
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ICS1893 Data Sheet - Release 7.5.4 10Base-T Operation: Idle An ICS1893 transmits Normal Link Pulses (that is, 10Base-T Idles) on its MDI in the absence of data (that is, when the MAC/repeater is not requiring it to transmit any data). ...
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... In 10Base-T mode, an ICS1893 appends an IDL to the end of each packet during data transmission. The receiving PHY (that is, the remote link partner) sees this IDL and removes it from the data stream. 7.5.7 10Base-T Operation: Carrier Detection The ICS1893 has a 10Base-T Carrier Detection Function that establishes the state of its Carrier Sense signal (CRS), based upon the state of its Transmit and Receive state machines ...
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ICS1893 Data Sheet - Release 7.5.9 10Base-T Operation: Jabber The ICS1893 has an ISO/IEC compliant Jabber Detection Function that, when enabled, monitors the data stream sent to its Twisted-Pair Transmitter to ensure that it does not exceed the 10Base-T Jabber ...
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ICS1893 - Release 7.5.11 10Base-T Operation: Twisted-Pair Transmitter The 10Base-T Twisted-Pair Transmitter is functionally similar to the 100Base-TX Twisted-Pair Transmitter. The primary differences are in the data rate and signaling, as specified in the ISO/IEC specifications. For more information, see ...
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... The Serial Management Interface is a synchronous, bi-directional, two-wire, serial interface for the exchange of configuration, control, and status data between a PHY, such as an ICS1893, and an STA. All data transferred on an MDIO signal is synchronized by its MDC signal. The PHY and STA exchange data through a pre-defined register set ...
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... The ability to process Management Frames that do not have a preamble is provided by the Management Frame Preamble Suppression bit, (bit 1.6 in the ICS1893’ s Status Register). This is an ISO/IEC defined status bit that is intended to provide an indication of whether or not a PHY supports the MF Preamble Suppression feature. In order to maintain backward compatibility with the ICS1890, which did not support MF Preamble Suppression, the ICS1893 MF Preamble Suppression bit is a Command Override Write bit which defaults to a logic zero ...
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ICS1893 Data Sheet - Release 7.6.2.7 Management Frame Turnaround A valid management frame includes a turn-around field (TA), which is a 2-bit time space between the REGAD field and the Data field. This time allows an ICS1893 and an STA ...
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... Section 8.3, “ Register 1: Status Register” • Section 8.4, “ Register 2: PHY Identifier Register” • Section 8.5, “ Register 3: PHY Identifier Register” • Section 8.6, “ Register 4: Auto-Negotiation Register” • Section 8.7, “ Register 5: Auto-Negotiation Link Partner Ability Register” ...
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... This section outlines the ICS1893 Management Register set. Management Register Set that the ICS1893 implements. Table 8-1. ISO/IEC-Specified Management Register Set Register Address 0 Control 1 Status 2,3 PHY Identifier 4 Auto-Negotiation Advertisement 5 Auto-Negotiation Link Partner Ability 6 Auto-Negotiation Expansion 7 Auto-Negotiation Next Page Transmit 8 Auto-Negotiation Next Page Link Partner Ability ...
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... For some bits, the default value depends on the state (that is, the logic value particular pin at reset (that is, the logic value of a pin is latched at reset). An example of pins that have a default condition that depends on the state of the pin at reset are the PHY / LED pins (P0AC, P1CL, P2LI, P3TD, and P4RD) discussed in the following sections: • ...
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ICS1893 Data Sheet - Release 8.1.4 Management Register Bit Special Functions This section discusses the types of special functions for the Management Register bits. 8.1.4.1 Latching High Bits The purpose of a latching high (LH) bit is to record an ...
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... IEEE reserved 0.1 IEEE reserved 0.0 IEEE reserved † Whenever the PHY address of • Is equal to 00000 (binary), the Isolate bit 0.10 is logic one. • Is not equal to 00000, the Isolate bit 0.10 is logic zero. ‡ As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value to all Reserved bits ...
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ICS1893 Data Sheet - Release 8.2.2 Loopback Enable (bit 0.14) This bit controls the Loopback mode for the ICS1893. Setting this bit to logic: • Zero disables the Loopback mode. • One enables the Loopback mode by disabling the Twisted-Pair ...
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... Serial Management Interface continues to operate normally (that is, bit 0.10 does not affect the Management Interface). The default value for bit 0.10 depends upon the PHY address of • Is equal to 00000b, then the default value of bit 0.10 is logic one, and the ICS1893 isolates itself from the MAC/Repeater Interface. • ...
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ICS1893 Data Sheet - Release 8.2.8 Duplex Mode (bit 0.8) This bit provides a means of controlling the ICS1893 Duplex Mode. Its operation depends on several other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12). ...
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... No remote fault detected Remote fault detected N/A Always 1: PHY has Auto-Negotiation ability Link is invalid/down Link is valid/established No jabber condition Jabber condition detected N/A Always 1: PHY has extended capabilities Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. 67 Chapter 8 Management Register Set . Ac- SF De- Hex ...
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ICS1893 Data Sheet - Release 8.3.2 100Base-TX Full Duplex (bit 1.14) The STA reads this bit to learn if the ICS1893 can support 100Base-TX, full-duplex operations. The ISO/IEC specification requires that the ICS1893 must set bit 1.14 to logic: • ...
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ICS1893 - Release 8.3.6 IEEE Reserved Bits (bits 1.10:7) The IEEE reserves these bits for future use. When an STA: • Reads a reserved bit, the ICS1893 returns a logic zero. • Writes a reserved bit, the STA must use ...
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ICS1893 Data Sheet - Release 8.3.9 Remote Fault (bit 1.4) An STA reads bit 1.4 to determine if a Remote Fault exists. The ICS1893 sets bit 1.4 based on the Remote Fault bit received from its remote link partner. The ...
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ICS1893 - Release 8.3.11 Link Status (bit 1.2) The purpose of this bit 1.2 (which is also accessible through the QuickPoll Detailed Status Register, bit 17. determine if an established link is dropped, even momentarily. To indicate a ...
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... Manufacturer’ s PHY Revision Number, discussed in All of the bits in the two PHY Identifier Registers are Command Override Write bits. An STA can read them at any time without condition. However, an STA can modify these register bits only when the Command Register Override bit (bit 16.15) is enabled with a logic one. ...
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ICS1893 - Release IEEE-Assigned Organizationally Unique Identifier (OUI) For each manufacturing organization, the IEEE assigns an 3-octet OUI. For Integrated Circuit Systems, Inc. the IEEE-assigned 3-octet OUI is 00A0BEh. The binary representation of an OUI is formed by expressing each ...
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... Manufacturer’ s PHY Revision Number All the bits in the two PHY Identifier Registers are Command Override Write bits. An STA can read them at any time without condition. However, An STA can modify these register bits only when the Command Register Override bit (bit 16.15) is enabled with a logic one. ...
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ICS1893 - Release 8.5.2 Manufacturer's Model Number (bits 3.9:4) The model number for the ICS1893 is 4 (decimal stored in bit 3.9:4 as 00100b. 8.5.3 Revision Number (bits 3.3:0) Table 8-10 lists the valid ICS1893 revision numbers, which ...
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... ICS1893 advertises (that is, exchanges) capability data with its remote link partner by using a pre-defined Link Code Word. The Link Code Word is embedded in the Fast Link Pulses exchanged between PHYs when the ICS1893 has its Auto-Negotiation sublayer enabled. The value of the Link Control Word is established based on the value of the bits in this register ...
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ICS1893 - Release 8.6.2 IEEE Reserved Bit (bit 4.14) The ISO/IEC specification reserves this bit for future use. However, the ISO/IEC Standard also defines bit 4.14 as the Acknowledge bit. When this reserved bit is read by an STA, the ...
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ICS1893 Data Sheet - Release 8.6.5 Technology Ability Field (bits 4.9:5) When its Auto-Negotiation sublayer is enabled, the ICS1893 transmits its link capabilities to its remote link partner during the auto-negotiation process. The Technology Ability Field (TAF) bits 4.12:5 determine ...
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ICS1893 - Release 8.6.5.2 Technology Ability Field: Software Mode In Software mode (that is, the HW/SW pin is logic one), these TAF bits are Command Override Write bits. The default value of these bits depends on the signal level on ...
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ICS1893 Data Sheet - Release 8.7 Register 5: Auto-Negotiation Link Partner Ability Register Table 8-12 lists the bits for the Auto-Negotiation Link Partner Ability Register. An STA uses this register to determine the capabilities being advertised by the remote link ...
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ICS1893 - Release 8.7.2 Acknowledge (bit 5.14) The ISO/IEC specification defines bit 5.14 as the Acknowledge bit. When this bit is a: • Zero, it indicates that the remote link partner has not received the ICS1893 Link Control Word. • ...
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ICS1893 Data Sheet - Release 8.8 Register 6: Auto-Negotiation Expansion Register Table 8-13 lists the bits for the Auto-Negotiation Expansion Register, which indicates the status of the Auto-Negotiation process. Note: For an explanation of acronyms used in Table 8-13. Auto-Negotiation ...
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ICS1893 - Release 8.8.2 Parallel Detection Fault (bit 6.4) The ICS1893 sets this bit to a logic one if a parallel detection fault is encountered. A parallel detection fault occurs when the ICS1893 cannot disseminate the technology being used by ...
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ICS1893 Data Sheet - Release 8.9 Register 7: Auto-Negotiation Next Page Transmit Register Table 8-14 lists the bits for the Auto-Negotiation Next Page Transmit Register, which establishes the contents of the Next Page Link Control Word that is transmitted during ...
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... ICS1893 - Release 8.9.1 Next Page (bit 7.15) This bit is used by a PHY/STA to enable the transmission of Next Pages following the base Link Control Word as long as the remote link partner supports the Next Page features of Auto-Negotiation. This bit is used to establish the state of the Next Page (NP) bit of the Next Page Link Control Word (that is, the NP bit of the Next Page Link Control Word tracks this bit) ...
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ICS1893 Data Sheet - Release 8.10 Register 8: Auto-Negotiation Next Page Link Partner Ability Register Table 8-15 lists the bits for the Auto-Negotiation Next Page Link Partner Ability Register, which establishes the contents of the Next Page Link Control Word ...
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... ICS1893 - Release 8.10.1 Next Page (bit 8.15) This bit is used by a PHY/STA to enable the transmission of Next Pages following the base Link Control Word as long as the remote link partner supports the Next Page features of Auto-Negotiation. This bit is used to establish the state of the Next Page (NP) bit of the Next Page Link Control Word (that is, the NP bit of the Next Page Link Control word tracks this bit) ...
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... ICS reserved 16.10 PHY Address Bit 4 16.9 PHY Address Bit 3 16.8 PHY Address Bit 2 16.7 PHY Address Bit 1 16.6 PHY Address Bit 0 16.5 Stream Cipher Test Mode Normal operation 16.4 ICS reserved 16.3 NRZ/NRZI encoding 16.2 Transmit invalid codes 16.1 ICS reserved 16 ...
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... PHY Address (bits 16.10:6) These five bits hold the Serial Management Port Address of the ICS1893. During either a hardware reset or a power-on reset, the PHY address is read from the LED interface. (For information on the LED interface, see Section 6.8, “ Status Interface” ...
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ICS1893 Data Sheet - Release 8.11.7 Invalid Error Code Test (bit 16.2) The Invalid Error Code Test bit allows an STA to force the ICS1893 to transmit symbols that are typically classified as invalid. The purpose of this test bit ...
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ICS1893 - Release 8.12 Register 17: Quick Poll Detailed Status Register Table 8-18 lists the bits for the Quick-Poll Detailed Status Register. This register is a 16-bit read-only register used to provide an STA with detailed status of the ICS1893 ...
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ICS1893 Data Sheet - Release 8.12.1 Data Rate (bit 17.15) The Data Rate bit indicates the ‘ selected technology’ the ICS1893 is in: • Hardware mode, the value of this bit is determined by the 10/100SEL input pin. ...
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ICS1893 - Release 8.12.3 Auto-Negotiation Progress Monitor (bits 17.13:11) The Auto-Negotiation Progress Monitor consists of the Auto-Negotiation Complete bit (bit 17.4) and the three Auto-Negotiation Monitor bits (bits 17.13:11). The Auto-Negotiation Progress Monitor continually examines the state of the Auto-Negotiation ...
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ICS1893 Data Sheet - Release 8.12.5 100Base PLL Lock Error (bit 17.9) The Phase-Locked Loop (PLL) Lock Error bit indicates to an STA whether the ICS1893 has ever experienced a PLL Lock Error. A PLL Lock Error occurs when the ...
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ICS1893 - Release 8.12.8 Halt Symbol (bit 17.6) The Halt Symbol bit indicates to an STA the detection of a Halt Symbol in a 100Base data stream by the ICS1893. During reception of a valid packet, the ICS1893 examines each ...
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ICS1893 Data Sheet - Release 8.12.12 Jabber Detect (bit 17.2) Bit 17.2 is functionally identical to bit 1.1. The Jabber Detect bit indicates whether a jabber condition has occurred. This bit is a 10Base-T function. 8.12.13 Remote Fault (bit 17.1) ...
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ICS1893 - Release 8.13 Register 18: 10Base-T Operations Register The 10Base-T Operations Register provides an STA with the ability to monitor and control the ICS1893 activity while the ICS1893 is operating in 10Base-T mode. Note: 1. For an explanation of ...
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ICS1893 Data Sheet - Release 8.13.2 Polarity Reversed (bit 18.14) The Polarity Reversed bit is used to inform an STA whether the ICS1893 has detected that the signals on the Twisted-Pair Receive Pins (TP_RXP and TP_RXN) are reversed. When the ...
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ICS1893 - Release 8.13.8 Link Loss Inhibit (bit 18.1) The Link Loss Inhibit bit allows an STA to prevent the ICS1893 from dropping the link in 10Base-T mode. When an STA sets this bit to logic: • Zero, the state ...
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ICS1893 Data Sheet - Release 8.14 Register 19: Extended Control Register 2 The Extended Control Register provides more refined control of the internal ICS1893 operations. Note: 1. For an explanation of acronyms used in 2. During any write operation to ...
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ICS1893 - Release 8.14.1 Node/Repeater Configuration (bit 19.15) The Node/Repeater Configuration bit directly indicates the state of the NOD/REP input pin. When this bit is logic: • Zero, the NOD/REP input pin is pulled down, which instructs the operation code ...
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ICS1893 Data Sheet - Release 8.14.5 Twisted Pair Tri-State Enable, TPTRI (bit 19.7) The ICS1893 provides a Twisted Pair Tri-State Enable bit. This bit forces the TP_TXP and TP_TXN signals to a high-impedance state. When this bit is set to ...
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ICS1893 - Release Chapter 9 Pin Diagram, Listings, and Descriptions 9.1 ICS1893 Pin Diagram NOD/REP 1 10/100SEL 2 TP_CT 3 VSS 4 TP_TXP 5 TP_TXN 6 VDD 7 VDD 8 10TCSR 9 100TCSR 10 VSS 11 VSS 12 TP_RXP 13 ...
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ICS1893 Data Sheet - Release 9.2 ICS1893 Pin Listings Table 9-1 lists the ICS1893 pins by pin number. Table 9-1. ICS1893 Pins, by Pin Number Pin Pin Name No. 1 NOD/REP 2 10/100SEL 3 TP_CT 4 VSS 5 TP_TXP 6 ...
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ICS1893 - Release 9.3 ICS1893 Pin Descriptions The tables in this section list the ICS1893 pins by their functional grouping. 9.3.1 Transformer Interface Pins Table 9-2 lists the pins for the transformer interface group of pins. Table 9-2. Transformer Interface ...
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... ICS1893 Data Sheet - Release 9.3.2 Multi-Function (Multiplexed) Pins: PHY Address and LED Pins Table 9-3 lists the pins for the multi-function group of pins (that is, the multiplexed PHY Address / LED pins). Note: 1. During either a power-on reset or a hardware reset, each multi-function configuration pin is an input that is sampled when the ICS1893 exits the reset state ...
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... The ICS1893 asserts its Collision LED for a period of approximately 70 msec when it detects a collision. Caution: This pin must not float. (See the notes at “ Multi-Function (Multiplexed) Pins: PHY Address and LED Pins” .) Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. ...
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... De-asserted, this state indicates the ICS1893 does not have a link. – Asserted, this state indicates the ICS1893 has a valid link. Caution: This pin must not float. (See the notes at “ Multi-Function (Multiplexed) Pins: PHY Address and LED Pins” .) Copyright © 2000, Integrated Circuit Systems, Inc. ...
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... LED directly. Caution: This pin must not float. (See the notes at “ Multi-Function (Multiplexed) Pins: PHY Address and LED Pins” .) Copyright © 2000, Integrated Circuit Systems, Inc. All rights reserved. ...
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ICS1893 Data Sheet - Release 9.3.3 Configuration Pins Table 9-4 lists the configuration pins. Table 9-4. Configuration Pins Pin Pin Name Number Type 10/100SEL 2 Input or Output 10TCSR 9 Input 100TCSR 10 Input ANSEL 26 Input or Output DPXSEL ...
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ICS1893 - Release Table 9-4. Configuration Pins (Continued) Pin Pin Name Number Type HW/SW 23 Input LOCK 27 Output LSTA 21 Output MII/SI 19 Input NOD/REP 1 Input REF_IN 53 Input REF_OUT 52 Input RESETn 18 Input ICS1893 Rev C ...
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ICS1893 Data Sheet - Release 9.3.4 MAC/Repeater Interface Pins This section lists pin descriptions for each of the following interfaces • Section 9.3.4.1, “ MAC/Repeater Interface Pins for Media Independent Interface” • Section 9.3.4.2, “ MAC/Repeater Interface Pins for 100M ...
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ICS1893 - Release Table 9-5. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type MDIO 30 Input/ Output RXCLK 38 Output ICS1893 Rev C 6/6/00 Chapter 9 Pin Diagram, Listings, and Descriptions Pin Description Management ...
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... Low, the MAC indicates that it is not in a tri-state condition. • High, the MAC indicates that tri-state condition. In this case, the ICS1893 acts to ensure that only one PHY is active at a time. Transmit Clock. The ICS1893 generates this clock signal to synchronize the transfer of data from the MAC/Repeater Interface to the ICS1893. When the mode is: • ...
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ICS1893 - Release Table 9-5. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type TXEN 44 Input TXER 42 Input ICS1893 Rev C 6/6/00 Chapter 9 Pin Diagram, Listings, and Descriptions Pin Description Transmit Enable. ...
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ICS1893 Data Sheet - Release 9.3.4.2 MAC/Repeater Interface Pins for 100M Symbol Interface Table 9-6 lists the MAC/Repeater Interface pin descriptions for the 100M Symbol Interface. Table 9-6. MAC/Repeater Interface Pins: 100M Symbol Interface MII Pin 100M Pin Name Symbol ...
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ICS1893 - Release Table 9-6. MAC/Repeater Interface Pins: 100M Symbol Interface (Continued) MII Pin 100M Pin Name Symbol No. Pin Name RXCLK SRCLK 38 ICS1893 Rev C 6/6/00 Chapter 9 Pin Diagram, Listings, and Descriptions Pin Type Output (Symbol) Receive ...
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... Low, the MAC indicates it is not in a tri-state condition. • High, the MAC indicates tri-state condition. In this case, the ICS1893 acts to ensure that only one PHY is active at a time. (A PHY address of 00 also tri-states the MII interface.) Output Symbol Transmit Clock. ...
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ICS1893 - Release 9.3.4.3 MAC/Repeater Interface Pins for 10M Serial Interface Table 9-7 lists the MAC/Repeater Interface pin descriptions for the 10M Serial Interface. Table 9-7. MAC/Repeater Interface Pins: 10M Serial Interface MII Pin 100M Pin Name Symbol No. Pin ...
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... High, the MAC indicates that tri-state condition. In this case, the ICS1893 acts to ensure that only one PHY is active at a time. • If the PHY address is 00, the ICS1893 acts as if the RX-TRI pin is held high. Output 10M (Serial Interface) Transmit Clock. ...
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ICS1893 - Release 9.3.5 Reserved Pins Table 9-8 lists the reserved pins. Table 9-8. Reserved Pins Pin Pin Pin Name Number Type NC 20 – ICS1893 Rev C 6/6/00 Chapter 9 Pin Diagram, Listings, and Descriptions Pin Description No Connect. ...
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ICS1893 Data Sheet - Release 9.3.6 Ground and Power Pins Table 9-9 lists the ground and power pins. Table 9-9. Ground and Power Pins Pin Name Pin Number VSS 4 VSS 11 VSS 12 VSS 17 VSS 22 VSS 28 ...
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ICS1893 - Release Chapter 10 DC and AC Operating Conditions 10.1 Absolute Maximum Ratings Table 10-1 lists absolute maximum ratings. Stresses above these ratings can permanently damage the ICS1893. These ratings, which are standard values for ICS commercially rated parts, ...
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ICS1893 Data Sheet - Release 10.3 Recommended Component Values Table 10-3. Recommended Component Values for ICS1893 Parameter Oscillator Frequency 10TCSR Resistor Value 100TCSR Resistor Value LED Resistor Value † There are two IEEE Std 802.3 requirements that drive the tolerance ...
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ICS1893 - Release 10.4 DC Operating Characteristics This section lists the ICS1893 DC operating characteristics. 10.4.1 DC Operating Characteristics for Supply Current Table 10-4 lists the DC operating characteristics for the supply current to the ICS1893 under various conditions. Note: ...
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ICS1893 Data Sheet - Release 10.4.3 DC Operating Characteristics for REF_IN Table 10-6 lists the 3.3-V DC characteristics for the REF_IN pin. Note: The REF_IN input switch point is 50% of VDD. Table 10-6. 3.3-V DC Operating Characteristics for REF_IN ...
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ICS1893 - Release 10.5 Timing Diagrams 10.5.1 Timing for Clock Reference In (REF_IN) Pin Table 10-8 lists the significant time periods for signals on the clock reference in (REF_IN) pin. shows the timing diagram for the time periods. Note: The ...
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ICS1893 Data Sheet - Release 10.5.2 Timing for Transmit Clock (TXCLK) Pins Table 10-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various interfaces. Figure 10-3 shows the timing diagram for the time ...
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ICS1893 - Release 10.5.3 Timing for Receive Clock (RXCLK) Pins Table 10-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various interfaces. Figure 10-4 shows the timing diagram for the time periods. Table ...
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ICS1893 Data Sheet - Release 10.5.4 100M MII / 100M Stream Interface: Synchronous Transmit Timing Table 10-11 lists the significant time periods for the 100M MII / 100M Stream Interface synchronous transmit timing. The time periods consist of timings of ...
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ICS1893 - Release 10.5.5 10M MII: Synchronous Transmit Timing Table 10-12 lists the significant time periods for the 10M MII synchronous transmit timing. The time periods consist of timings of signals on the following pins: • TXCLK • TXD[3:0] • ...
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ICS1893 Data Sheet - Release 10.5.6 MII / 100M Stream Interface: Synchronous Receive Timing Table 10-13 lists the significant time periods for the MII / 100M Stream Interface synchronous receive timing. The time periods consist of timings of signals on ...
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ICS1893 - Release 10.5.7 MII Management Interface Timing Table 10-14 lists the significant time periods for the MII Management Interface timing (which consists of timings of signals on the MDC and MDIO pins). Table 10-14. MII Management Interface Timing Time ...
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ICS1893 Data Sheet - Release 10.5.8 10M Serial Interface: Receive Latency Table 10-15 lists the significant time periods for the 10M Serial Interface timing. The time periods consist of timings of signals on the following pins: • TP_RX (the MDI ...
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ICS1893 - Release 10.5.9 10M Media Independent Interface: Receive Latency Table 10-16 lists the significant time periods for the 10M MII timing. The time periods consist of timings of signals on the following pins: • TP_RX (that is, the MII ...
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ICS1893 Data Sheet - Release 10.5.10 10M Serial Interface: Transmit Latency Table 10-17 lists the significant time periods for the 10M Serial Interface transmit latency. The time periods consist of timings of signals on the following pins: • 10TXEN (the ...
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ICS1893 - Release 10.5.11 10M Media Independent Interface: Transmit Latency Table 10-18 lists the significant time periods for the 10M MII transmit latency. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • ...
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ICS1893 Data Sheet - Release 10.5.12 MII / 100M Stream Interface: Transmit Latency Table 10-19 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time periods consist of timings of signals on the following ...
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ICS1893 - Release 10.5.13 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 10-20 lists the significant time periods for the 100M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: • TXEN ...
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ICS1893 Data Sheet - Release 10.5.14 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 10-21 lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: ...
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ICS1893 - Release 10.5.15 100M MII / 100M Stream Interface: Receive Latency Table 10-22 lists the significant time periods for the 100M MII / 100M Stream Interface receive latency. The time periods consist of timings of signals on the following ...
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ICS1893 Data Sheet - Release 10.5.16 100M Media Dependent Interface: Input-to-Carrier Assertion/De-Assertion Table 10-23 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time periods consist of timings of signals on the following pins: • TP_RX (that ...
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ICS1893 - Release 10.5.17 Reset: Power-On Reset Table 10-24 lists the significant time periods for the power-on reset. The time periods consist of timings of signals on the following pins: • VDD • TXCLK Figure 10-18 shows the timing diagram ...
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ICS1893 Data Sheet - Release 10.5.18 Reset: Hardware Reset and Power-Down Table 10-25 lists the significant time periods for the hardware reset and power-down reset. The time periods consist of timings of signals on the following pins: • REF_IN • ...
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ICS1893 - Release 10.5.19 10Base-T: Heartbeat Timing (SQE) Table 10-26 lists the significant time periods for the 10Base-T heartbeat (that is, the Signal Quality Error). The time periods consist of timings of signals on the following pins: • TXEN • ...
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ICS1893 - Release 10.5.20 10Base-T: Jabber Timing Table 10-27 lists the significant time periods for the 10Base-T jabber. The time periods consist of timings of signals on the following pins: • TXEN • TP_TX (that is, TP_TXP and TP_TXN) • ...
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ICS1893 - Release 10.5.21 10Base-T: Normal Link Pulse Timing Table 10-28 lists the significant time periods for the 10Base-T Normal Link Pulse (which consists of timings of signals on the TP_TXP pins). Table 10-28. 10Base-T Normal Link Pulse Timing Time ...
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ICS1893 Data Sheet - Release 10.5.22 Auto-Negotiation Fast Link Pulse Timing Table 10-29 lists the significant time periods for the ICS1893 Auto-Negotiation Fast Link Pulse. The time periods consist of timings of signals on the following pins: • TP_TXP • ...
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... ICS1893 - Release Chapter 11 Physical Dimensions of ICS1893 Package This section gives the physical dimensions for the ICS1893 package. • The lead count ( leads. • The nominal footprint (that is the body) is 10.0 mm. Table 11-1 lists the ICS1893 physical dimensions, which are shown in Table 11-1. ...
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... Figure 11-1. ICS1893 Physical Dimensions ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ...
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... ICS1893 - Release Chapter 12 Ordering Information Figure 12-1 shows ordering information for the ICS1893 package: • ICS1893Y-10LF and ICS1893YI-10LF (industrial temp.) Figure 12-1. ICS1893 Ordering Information Y -10 ICS 1893 ICS1893 Rev C 6/6/ Tape and Reel Lead (Pb) Free, RoHS compliant Package Type Y- TQFP (Thin Quad Flat Pack) ...
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Integrated Circuit Systems, Inc. Corporate Headquarters: Silicon Valley: Web Site: ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device ...