5AGZME5H2F35C3N Altera Corporation, 5AGZME5H2F35C3N Datasheet - Page 24
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5AGZME5H2F35C3N
Manufacturer Part Number
5AGZME5H2F35C3N
Description
FPGA - Field Programmable Gate Array FPGA - Arria V GZ 15096 LABS 534 IOs
Manufacturer
Altera Corporation
Series
Arria V GZr
Datasheet
1.5AGXFB3H4F40C5N.pdf
(33 pages)
Specifications of 5AGZME5H2F35C3N
Rohs
yes
Number Of Logic Blocks
15096
Number Of I/os
534
Maximum Operating Frequency
800 MHz
Operating Supply Voltage
1.2 V to 1.8 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
FBGA-1152
Distributed Ram
33518 kbit
Minimum Operating Temperature
0 C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
5AGZME5H2F35C3N
Manufacturer:
ALTERA
Quantity:
3 000
Altera Corporation
24
PMA Features
PCS Features
Table 20: PMA Features of the Transceivers in Arria V Devices
Backplane support
Chip-to-chip support
PLL-based clock recovery
Programmable serializer and
deserializer (SERDES)
Equalization and pre-emphasis
Ring oscillator transmit PLLs
LC oscillator ATX transmit PLLs
(Arria V GZ devices only)
Input reference clock range
Transceiver dynamic
reconfiguration
To prevent core and I/O noise from coupling into the transceivers, the PMA block is isolated from the rest
of the chip—ensuring optimal signal integrity. For the transceivers, you can use the channel PLL of an unused
receiver PMA as an additional transmit PLL.
The Arria V core logic connects to the PCS through an 8, 10, 16, 20, 32, 40, 64, 66, or 67 bit interface,
depending on the transceiver data rate and protocol. Arria V devices contain PCS hard IP to support
PCIe Gen1, Gen2, and Gen3, GbE, Serial RapidIO
All other standard and proprietary protocols within the following speed ranges are also supported:
Arria V Device Overview
611 Mbps to 6.5536 Gbps—supported through the custom double-width mode (up to 6.5536 Gbps) and
custom single-width mode (up to 3.75 Gbps) of the transceiver PCS hard IP.
6.5536 Gbps to 10.3125 Gbps—supported through dedicated 80 or 64 bit interface that bypass the PCS
hard IP and connects the PMA directly to the core logic. In Arria V GZ, this is supported in the transceiver
PCS hard IP.
Features
Superior jitter tolerance
Flexible SERDES width
611 Mbps to 10.3125 Gbps
600 Mbps to 12.5 Gbps
27 MHz to 710 MHz
Allows the reconfiguration of a single channel without affecting the
operation of other channels
Arria V GX, GT, SX, and ST devices—Driving capability at 6.5536 Gbps
with up to 25 dB channel loss
Arria V GZ devices—Driving capability at 12.5 Gbps with up to 16 dB
channel loss
Arria V GX, GT, SX, and ST devices—Up to 10.3125 Gbps
Arria V GZ devices—Up to 12.5 Gbps
Arria V GX, GT, SX, and ST devices—Up to 14.37 dB of pre-emphasis
and up to 4.7 dB of equalization
Arria V GZ devices—4-tap pre-emphasis and de-emphasis
®
(SRIO), GPON, and CPRI.
Capability
Arria V Device Overview
2013.01.11
AV-51001